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http://dx.doi.org/10.9708/jksci.2015.20.2.001

Design of High-Speed Parallel Multiplier on Finite Fields GF(3m)  

Seong, Hyeon-Kyeong (School of Computer Information Communication Eng., Sangji University)
Publication Information
Journal of the Korea Society of Computer and Information / v.20, no.2, 2015 , pp. 1-10 More about this Journal
Abstract
In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields $GF(3^m)$, and design the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $(m+1)^2$ same basic cells. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $T_A+T_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.
Keywords
Finite fields; Multiplier; Irreducible polynomial; Polynomial; GF;
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Times Cited By KSCI : 2  (Citation Analysis)
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1 K. C. Smith. "The Prospect for Multivalued Logic : A Technology and Applications View," IEEE Trans. Computers, Vol. C-30, No. 9, pp. 619-634, Sept. 1981.   DOI   ScienceOn
2 M. Kameyama and T. Higuchi, "Multiple-Valued Logic and Special Purpose Processors : Overview and Future," in Proc. IEEE Int. Symp. Multiple-Valued Logic, pp. 289-292, 1982.
3 S .L. Hurst, "Multiple-valued Logic-its Future," IEEE Trans. Computers, Vol 30, pp. 1161-1179, Dec. 1984.
4 M. A. Hasan, M. Wang, and V. K. Bhargava, "Moduler Construction of Low Complexity Parallel Multipliers for a Class of Finite Fields $GF(2^m)$," IEEE Trans. Computers, Vol. 41, No. 8, pp. 961-971, Aug. 1992.
5 3rd Generation Partnership Project., "Technical specification group GSM/EDGE radio access network; channel coding (release 5)," Tech. Rep. 3GPP TS 45.003 V5.6.0, June 2003.
6 C. K. Koc, and B. Sunar, "Low Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields," IEEE Trans. Computers, Vol. 47, No. 3, pp. 353-356, Mar. 1998.   DOI   ScienceOn
7 A. Halbutogullari and C. K. Koc, "Mastrovito Multiplier for General Irreducible Polynomials," IEEE Trans. Computers, Vol. 49, No. 5, pp. 503-518, May 2000.   DOI   ScienceOn
8 C. Y. Lee, E. H. Lu, and J. Y. Lee, "Bit Parallel Systolic Multipliers for $GF(2^m)$ Fields Defined by All-One and Equally Spaced Polynomials," IEEE Trans. Computers, Vol. 50, No. 5, pp. 385-392, May 2001.   DOI   ScienceOn
9 T. W. Kim, W. J. Lee, and K. W. Kim, "Bit-Parallel Systolic Multiplication Architecture with Low Complexity and Latency in $GF(2^m)$ Using Irreducible AOP," Journal of KIIT, Vol. 11, No. 3, pp. 133-139, March 2013.
10 K. W. Kim and J. C. Jeon, "Montgomery Multiplication Architecture Based on Cellular Systolic Array over $GF(2^m)$," Journal of KIIT, Vol. 10, No. 9, pp. 1-6, Sept. 2013.
11 N. S Chang, T. H. Kim, C. H. Kim, D. G. Han, and H. W. Kim, "Digit-Serial Finite Field Multipliers for $GF(2^m)$," Journal of IEIE, Vol. 45-SD, No. 10, pp. 23-30, Oct. 2008.
12 C. L. Wang and J. L. Lin, "Systolic Array Implementation of Multipliers for Finite Fields $GF(2^m)$," IEEE Trans. Circuits and Systems, Vol. 38, No. 7, July 1991.
13 S. W. Wei, "A Systolic Power-Sum Circuit for $GF(2^m)$," IEEE Trans. Computers, Vol. 43, No. 2, pp. 226-229, Feb. 1994.   DOI   ScienceOn