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Design of VLSI Architecture for Efficient Exponentiation on $GF(2^m)$  

한영모 (이화여자대학교 정보통신공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.41, no.6, 2004 , pp. 27-35 More about this Journal
Abstract
Finite or Galois fields have been used in numerous applications such as error correcting codes, digital signal processing and cryptography. These applications often require exponetiation on GF(2$^{m}$ ) which is a very computationally intensive operation. Most of the existing methods implemented the exponetiation by iterative methods using repeated multiplications, which leads to much computational load, or needed much hardware cost because of their structural complexity in implementing. In this paper, we present an effective VLSI architecture for exponentiation on GF(2$^{m}$ ). This circuit computes the exponentiation by multiplying product terms, each of which corresponds to an exponent bit. Until now use of this type algorithm has been confined to a primitive element but we generalize it to any elements in GF(2$^{m}$ ).
Keywords
Galois fields; exponenitator; VLSI; VHDL;
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