• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.7C
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• pp.658-666
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• 2007

In general, the earlier linear-phase MAXFLAT(maximally flat) lowpass FIR filters have the main disadvantage of a gain response in the half frequency band $(0{\leq}w{\leq}{\pi}/2)$ by the closed form transfer functions used in design techniques for realizing them. Moreover, most of them has existent problems as follows : ripple error in the stopband, gentle-cutoff attenuation, phase and group delay and inexact cutoff frequency response. It is due to the approximation algorithms such as Chebyshev norm and Remez exchange which are used to approach MAXFLAT and linear-phase characteristics in frequency domain. In this paper, a new mathematically closed-form transfer function is introduced for the design of MAXFLAT lowpass FIR filters which have the zero-phase and wideband-gain response. In addition, we verify that the closed-form transfer function is easily realized due to our generalized formulas derived newly by using MAXFLAT conditions including an arbitrary cutoff point. This method is, therefore, useful for "simple and quick designs". Conclusively, we propose a technique for the design of new zero-phase wideband MAXFLAT lowpass FIR filters which can achieve sharp-cutoff attenuation exceeding 250 dB almost everywhere.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.10
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• pp.1147-1158
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• 2008

In this paper, we designed a phase-looking circuit that locks the 16.8 GHz VTDRO to a 700 MHz SAW oscillator using SPD as a phase detector Direct phase locking with loop filter alone causes the problem of lock time, so VTDRO is phase leered by loop filter with the aid of time varying square wave current generator. The current generator is related to the loop filter and needs the systematic toning. In this paper, a systematic design of the current generator and loop filter is presented. The fabricated PLDRO shows a stabilized frequency of 16.8 GHz, a output power 6.3 dBm, and a phase noise of -101 dBc/Hz at the 100 kHz offset.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2387-2394
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• 2013

A low spur phase-locked loop (PLL) with FVCO-sampled feedforward loop-filter has been proposed. Conventional PLL has loop filter made of a resistor and capacitors. The proposed PLL is working stably with the filter consisted of capacitors and a switch. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process and proved by simulation with HSPICE.

• Proceedings of the Optical Society of Korea Conference
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• 2003.07a
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• pp.296-297
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• 2003

본 연구에서는 푸리에 변환법에 의한 위상정보 추출 기술을 개발하고, 주파수 영역에서의 창함수 필터에 따른 위상추출 특성을 분석하였다. 푸리에 변환법은 위상이동법과는 달리 정현파 패턴이 투영된 하나의 영상만을 이용하여 3차원 형상정보를 추출할 수 있는 장점이 있다. 획득된 영상은 오일러 공식으로부터 다음과 같이 표현할 수 있다. (중략)

• Journal of Broadcast Engineering
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• v.4 no.2
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• pp.134-143
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• 1999

In this paper, in order to implement the IDWT(inverse discrete wavelet transform) with relatively low complexity, we propose a VLSI architecture for odd-tap linear-phase IDWT filters. By considering the symmetric property of the linear phase filter, the input is added to the one located at symmetrical position of the filter before filtering. Then. we rearrange the delay line of the filter in a U-shaped fashion. requiring no global interconnection between the components. The proposed architecture for the IDWT filter consists of delay units. operator units, adder units. and postprocessor unit. Since each units are configured regularly and interconnected locally. the proposed architecture can accommodate arbitrary linear phase IDWTs by simply adding/removing the corresponding units. The M -level IDWT can be implemented by interconnecting the proposed architecture in a cascaded or semi-recursive form. It is expected that the proposed architecture for the IDWT can be effectively employed in the related area including MPEG-4, since the proposed architecture is less complex than the conventional architectures.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.497-500
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• 2003

In this paper, a new filter structure to improve frequency response characteristics in CIC(Cascaded Integrator-Comb) decimation filters is proposed. Conventional filters improve passband characteristics, but they make worse slinging band characteristics. In this paper, we propose a new filter which is called IFOP(Interpolated Fourth-Order Polynomials). By using this proposed filter, passband droop and aliasing band attenuation are simultaneously improved. Since proposed filter needs only one multiplication computation is not much. And overall linear phase characteristics are maintained since the proposed filter is also linear phase. Finally, implementation cost of the proposed filter is compared with those of conventional filters.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.6
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• pp.479-486
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• 2021

In this paper, an ultra small phase locked loop (PLL) with a single capacitor loop filter has been proposed by adding a signal sensing circuit (SSC). In order to extremely reduce the size of the PLL, the passive element loop filter, which occupies the largest area, is designed with a very small single capacitor (2pF). The proposed PLL is designed to operate stably by the output of the internal negative feedback loop including the SSC acting as a negative feedback to the output of the single capacitor loop filter of the external negative feedback loop. The SSC that detects the PLL output signal change reduces the excess phase shift of the PLL output frequency by adjusting the capacitance charge of the loop filter. Although the proposed structure has a capacitor that is 1/78 smaller than that of the existing structure, the jitter size differs by about 10%. The PLL is designed using a 1.8V 180nm CMOS process and the Spice simulation results show that it works stably.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.4
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• pp.591-598
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• 2021

The digital phase-locked loops(DPLL) is a circuit used for phase synchronization and has been generally used in various fields such as communication and circuit fields. State estimators are used to design digital phase-locked loops, and infinite impulse response state estimators such as the well-known Kalman filter have been used. In general, the performance of the infinite impulse response state estimator-based digital phase-locked loop is excellent, but a sudden performance degradation may occur in unexpected situations such as inaccuracy of initial value, model error, and disturbance. In this paper, we propose a minimum variance finite impulse response filter with optimal horizon for designing a new digital phase-locked loop. A numerical method is introduced to obtain the measured value interval length, which is an important parameter of the proposed finite impulse response filter, and to obtain a gain, the covariance matrix of the error is set as a cost function, and a linear matrix inequality is used to minimize it. In order to verify the superiority and robustness of the proposed digital phase-locked loop, a simulation was performed for comparison and analysis with the existing method in a situation where noise information was inaccurate.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.10
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• pp.1935-1940
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• 2016

This paper proposes a phase-locked loop (PLL) to minimize the loop filter output voltage fluctuation by using a comparator including RC time constant circuits. The voltage variation of loop filter is inputted to RC time constant circuits which have two RC time constants, large and small. While a small RC time constant circuit quickly conveys the output voltage variation of loop filter, a large RC time constant circuit conveys slowly the output voltage variation of loop filter and its output looks like constant voltage. The output signal of the comparator controls the sub charge pump and reduces the input voltage variation of voltage-controlled oscillator (VCO). Therefore, the proposed PLL generates a phase noise reduced signal. It has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.

• Transactions of the Korean Society of Mechanical Engineers
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• v.13 no.1
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• pp.67-76
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• 1989

Although the standard 2-CR network filter, one of the filters used for measuring surface roughness, is being used widely in the field of industry it possesses a weak point of causing Phase-distortion when the wavelength is passing through. Phase-corrected filter is used for eliminating these phase-distortion and the difference of phase characteristics between these two filters is thought to have considerable amount of effect on the surface roughness value. Moveover, the definition on this is as yet unclear. Therefore, the Rt and Rz value, obtained when the wavelength are passed through the standard and phase-corrected filters from the same random machine-processed surface, and its standard deviation are compared and experimented in this paper. Also, the ratio of relative bearing curve complying to the phase characteristics of these two filters are acquired. As a result, the use of phese-corrected filter is appropriate in experiments where the form of wavelength is important, and the standard deviation on the same experimented values appeared greater with when using the standard filter. The rate of relative bearing curve became greater as .lambda.$_{c}$, the cut-off value of filter, became smaller.r.