• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.5
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• pp.55-67
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• 1982

In this Paper new results relating to the acquisition behavior of a class of first-and secondorder digital phase-locked loops (DPLL) originally proposed by Reddy and Cupta are presented in the absence of noise. It has been found that the number of quantization levels L and the number of phase error states N play important roles in acquisition. For a given L-level quantizer, as N increases, the acquisition time increases, and the lock range decreases. However, the deviation of the steady state phase error decreases in this case. When L increases, the acquisition time decreases, and the lock range increases. However, variation of L affects little for the steady state phase error. In addition, the effects of a loop filter on acquisition have also been considered. One can get smaller acquisition time and larger lock range as the filter parameter value becomes larger. However, deviation of the steady state phase error increases in that case. Analytical results have been verified by computer simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.693-695
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• 2016

A random and systematic jitter suppressed DLL is presented. The AC averages the delay time of successive delay stages and equalizes the delay time of all delay stages. Measurement results of the DLL-based clock generator fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process shows 13.4-ps rms jitter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.301-306
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• 2005

In this paper, a gain-boosting charge pump(CP) and a latch type voltage controlled oscillato.(VCO) with voltage controlled resistor(VCR) were proposed. The gain-boosting CP achieves good .current matching of less than 11$mu$V voltage difference between 43$mu$V and 32$mu$V in its output range from 0.8V to 2.3V. The VCO with VCR shows good linear characteristics over the range from 1V to 3V. The fabricated VCO exhibits -108dBc/Hz phase noise at a 100kHz and is comparable to that of the integrated LC-tank oscillator. The phase locked loop(PLL) with new circuits was simulated in a 0.35$mu$m CMOS process and showed 150$mu$s locking time.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.3
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• pp.129-137
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• 2004

This paper presents a signature verification method that uses Gabor filter in computing similarity between signatures. In computing similarity to compare two on-line signatures, the temporal relationship between two signatures should be computed in advance. However, conventional point matching method using DP(dynamic programming) matching consumes much computation. In this paper, we propose a fast method for computing the temporal relationship between two on-line signatures by using the phase output of Gabor Inter applied on the on-line signature signals. Two similarity measures are defined in the method: Temporal Similarity and Temporally Arranged Feature Profile Similarity. With the proposed method, Ive could compare signatures 30 times faster than conventional method using DP matching.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.4
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• pp.55-60
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• 1983

A new type of digital phase-locked loop (DPLL) that employs a multilevel quantified timing error detector (TED) is proposed and analyzed under the assumption of negligible quantizing effect and no noise. Since the timing error is quantized uniformly, the TED has a linear characteristic. From the linear characteristic of TED, a first order difference equation describing the behavior of the loop is derived. Using the system equation, the loop is analyzed mathematically for phase step and frequency step input. Desired locking condition for the loop to be locked and the lock range for the DPLL's to achieve exact locking independently of initial conditions are ob-tained. And these analyses are confirmed by timing error plane plots and computer simulation.

• Journal of IKEEE
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• v.24 no.2
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• pp.441-445
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• 2020

A Permanent Magnet Synchronous Motor (PMSM) for an electrical power steering system (EPS) is adopting various dual three-phase type stator windings to get the high fault tolerance capability when the motor runs at the failure condition. In this paper, we analyze the effects of stator winding arrangements on the characteristics such as torque and efficiency of the PMSM with leading and lagging current angle variations using finite element method. As a result, the most valuable design criteria are proposed to select stator winding method. Especially, we suggest the most appropriate winding method in terms of torque and efficiency, extending constant output area and decreasing noise and torque ripples.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.2
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• pp.111-116
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• 2009

In this paper, we propose a phase offset estimation algorithm which is based on turbo coded digital broadcasting system. The phase estimator is an estimator outside turbo code decoder using LMS (Least Mean Square) algorithm to estimate the phase of next state. While the conventional LMS algorithm with a fixed step size is easy implemented, it has weak points that are difficult the channel estimation and tracking in the multipath environment. To resolve this problem, we propose new phase offset estimation method with a variable step size LMS (VS-LMS). Additionally, we propose a scheme which consists of a conventional LMS. The performance is verified by computer simulation according to a fixed phase offset and a increased phase offset, the proposed algorithm improve the bit error rate performance than the conventional algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.87-93
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• 2010

This paper presents a high resolution, wide input range 2-step time-to-digital converter used in digital PLL. TDC is used to compare the DPLL output frequency with reference frequency and should be implemented with high resolution to improve the phase noise of DPLL. The conventional TDC consists of delay line realized inverters, whose resolution is determined by delay time of inverter and transistor size, resulting in limited resolution. In this paper, 2-step TDC with phase-interpolation and Time Amplifier is proposed to meet the high resolution and wide input range by implement the delay time less than an inverter delay. The gain of Time Amplifier is improved by using the delay time difference between two inverters. It is implemented in $0.13{\mu}m$ CMOS process and the die area is $800{\mu}m{\times}850{\mu}m$ Current consumption is 12 mA at the supply voltage of 1.2 V. The resolution and input range of the proposed TDC are 0.357 ps and 200 ps, respectively.

• The Journal of the Acoustical Society of Korea
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• v.20 no.5
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• pp.92-99
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• 2001

To measure temporal variability of long- range transmission in northern part of the East Sea of Korea, low frequency acoustic sources were deployed on the continental shelf 0.4km south of Cape Shultz near the port of Vladivostok during October 1999. The transmissions of the phase modulated signals were recorded by VLA moored on the northern slope of Ulleung-do. The measured signals were processed for the acoustic arrivals and their variability in time. The temporal signal processing involves pulse compression of the phase-encoded signal, time spread and temporal coherence processing. Variability of the ocean sound speed field in time scales of short period seems to be dominated by random fluctuations caused by sound speed perturbation due to the vertical displacements associated with internal waves.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.5
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• pp.909-916
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• 2009

This paper presents the automatic vision algorithm to generate and calibrate reference phase plane to improve the accuracy of 3D measuring machine of using phase shifting projection moire method, which is not traditional N-bucket method, but is based on direct image processing method to the pattern projection image. Generally, to acquire accurate reference phase plane, the calibration specimen with well treated surface is needed, and detailed calibration method should be performed. For the cost reduction of specimen manufacturing and the calibration time reduction, on the specimen, not specially designed, with general accuracy level, an efficient calibration procedure for the reference phase generation is proposed. The proposed vision algorithm is developed to extract the line center points of the projected line pattern from acquired images, derive the line feature information consisting of its slope and intercept by using sampled feature points, and finally generate the related reference phase between line pairs. Experimental results show that the proposed method make reference phase plane with a good accuracy under noisy environment and the proposed algorithm can reduce the total cost to make high accurate calibration specimen, also increase the accuracy of reference phase plane, and reduce the complex calibration procedure to move grid via N-bucket algorithm precisely.