• Journal of the Korean Society of Manufacturing Process Engineers
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• v.12 no.2
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• pp.114-120
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• 2013

An EP(Electrolytic Polishing)-MAP(Magnetic Abrasive Polishing) hybrid process was applied to remove burr on the micro pattern. Micro pattern fabrication processes are combined with micro milling and EP-MAP hybrid process for deburring. Depending on the micro milling conditions which are applied, micro burrs are formed around the side and top of the pattern. The EP-MAP deburring is used to remove these burrs effectively. To optimize removal rate and form error in the EP-MAP hybrid process, a design of experiment was performed. The effect of deburring process and form error of micro pattern are evaluated via SEM images and the results of AFM.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.61-66
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• 2012

Chemical Mechanical Planarization (CMP) is a polishing process used in the microelectronic fabrication industries to achieve a globally planar wafer surface for the manufacturing of integrated circuits. Pad conditioning plays an important role in the CMP process to maintain a material removal rate (MRR) and its uniformity. For metal CMP process, highly acidic slurry containing strong oxidizer is being used. It would affect the conditioner surface which normally made of metal such as Nickel and its alloy. If conditioner surface is corroded, diamonds on the conditioner surface would be fallen out from the surface. Because of this phenomenon, not only life time of conditioners is decreased, but also more scratches are generated. To protect the conditioners from corrosion, thin organic film deposition on the metal surface is suggested without requiring current conditioner manufacturing process. To prepare the anti-corrosion film on metal conditioner surface, vapor SAM (self-assembled monolayer) and FC (Fluorocarbon) -CVD (SRN-504, Sorona, Korea) films were prepared on both nickel and nickel alloy surfaces. Vapor SAM method was used for SAM deposition using both Dodecanethiol (DT) and Perfluoroctyltrichloro silane (FOTS). FC films were prepared in different thickness of 10 nm, 50 nm and 100 nm on conditioner surfaces. Electrochemical analysis such as potentiodynamic polarization and impedance, and contact angle measurements were carried out to evaluate the coating characteristics. Impedance data was analyzed by an electrical equivalent circuit model. The observed contact angle is higher than 90o after thin film deposition, which confirms that the coatings deposited on the surfaces are densely packed. The results of potentiodynamic polarization and the impedance show that modified surfaces have better performance than bare metal surfaces which could be applied to increase the life time and reliability of conditioner during W CMP.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2007.05a
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• pp.368-370
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• 2007

AAO(Anodic Aluminum Oxidation) method has been known that it is practically useful for the fabrication of nano-structures and makes it possible to fabricate the highly ordered nano masters on large surface and even on the 2.5 or 3D surface at low cost comparing to the expensive e-beam lithography or the conventional silicon processing. In this study, by using the multi-step anodizing and etching processes, highly ordered nano patterned master with concave shapes was fabricated. By varying the processing parameters, such as initial matter and chemical conditions; electrical and thermal conditions; time scheduling; and so on, the size and the pitch of the nano pattern can be controlled. Consequently, various alumina/aluminum nano structures can be easily available in any size and shape by optimized anodic oxidation in various aqueous acids. The resulting good filled uniform nano molded structure through hot embossing molding process shows the validity of the fabricated nano pattern masters.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.935-938
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• 1997

Recently, the minimum line width shows a tendency to decrease and the multi-level increase in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. But there are several defects in CMP such as micro-scratches, abrasive contaminations, and non-uniformity of polished wafer edges. Wet etching include of Spin-etching can improve he defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(INterlayer-Dielectric) was removed by CMP and wet-etching methods in order to investigate the superiority of wet etching mechanism. In the thin film wafer, the results were evaluated at a viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And pattern step height was also compared for planarization characteristics of the patterned wafer.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.107-108
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• 2006

In this work, we first applied the chemical mechanical polishing (CMP) process to the planarization of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. $Bi_{3.25}La_{0.75}Ti_{3}O_{12}$ (BLT) ferroelectric film was fabricated by the sol-gel method. However, there have been serious problems in CMP in terms of repeatability and defects in patterned wafer. Especially, dishing & erosion defects increase the resistance because they decrease the interconnect section area, and ultimately reduce the lifetime of the semiconductor. Cross-sections of the wafer before and after CMP were examined by Scanning electron microscope(SEM). Process characteristics of non-dishing and erosion were investigated.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.11
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• pp.679-685
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• 2014

For the measurements of surface shape milled using FIB (focused ion beam), the silicon bulk, $Si_3N_4/Si$, and Al/Si samples are used and observed the shapes milled from different sputtering rates, incident angles of $Ga^+$ ions bombardment, beam current, and target material. These conditions also can be influenced the sputtering rate, raster image, and milled shape. The fundamental ion-solid interactions of FIB milling are discussed and explained using TRIM programs (SRIM, TC, and T-dyn). The damaged layers caused by bombarding of $Ga^+$ ions were observed on the surface of target materials. The simulated results were shown a little bit deviation with the experimental data due to relatively small sputtering rate on the sample surface. The simulation results showed about 10.6% tolerance from the measured data at 200 pA. On the other hand, the improved analytical model of damaged layer was matched well with experimental XTEM (cross-sectional transmission electron microscopy) data.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.371-371
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• 2013

사파이어 단결정 웨이퍼는 제조과정에서 결정 성장 조건 및 기계적 연마에 의하여 내부적인 결함이 발생할 수 있다. 사파이어 단결정은 일반적으로 LED용 기판 재료로 사용되며, 내부결함이 발생 시 기판 위의 GaN 등 layer의 결함도 함께 증가하므로 기판의 결함을 줄이는 과정이 중요한 이슈이다. 이 과정에 X-선 토포그래피는 단결정의 내부 결함을 모니터링 하는데 있어서 매우 유용한 방법이다. 이에 본 연구에서는 사파이어 단결정 웨이퍼에 내재하는 결함 형태를 X-선 Lang 토포그래피 방법(X-ray Lang Topography)으로 이미징하여 관찰, 분석하였다. Lang 토포그래피 방법은 X-선 투과법으로 넓은 부분을 우수한 강도와 분해능으로 내부 결함을 관찰할 수 있는 장점을 지니고 있다. X-선 source는 Mo $k{\alpha}$ 1을 사용하였으며, 시료는 c-plane 사파이어 웨이퍼를 사용하였다. 사파이어 웨이퍼의 (110), (102) 회절면의 X-선 토포그래피 이미지를 통해 전위 결함의 유형에 따른 이미지 패턴의 형성 메커니즘에 대해 연구하였고, 측정 회절면과 두께, 표면 데미지에 따른 전위 결함 이미지의 변화를 확인하였다. X-선 토포그래피 이미지를 통해 단결정 c-plane 사파이어 웨이퍼의 전위 결함의 형성 메카니즘 연구와 유형별 이미지와 회절면, 두께, 표면 데미지에 따른 이미지 변화 등을 확인하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.795-797
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• 2010

습식 식각은 식각용액으로서 화학용액을 사용하는 공정으로 반응물이 기판표면에서 화학반응을 일으켜 표면을 식각하는 과정이며, 표면결합의 제거를 위한 식각연마와 폴리싱을 위한 식각, 그리고 구조적 형상 패턴등이 있다. 여기서 화학용액은 산화제 또는 환원제 역할을 하는 혼합용액으로 구성된다. 습식 식각 시 수${\mu}m$의 해상도를 얻기 위해서는 그 부식액의 조성이나, 에칭시간, 부식액의 온도 등을 고려하여야 한다. 또한 습식 식각 후 포토 레지스트를 제거하는 과정에서 포토 레지스트를 깨끗이 제거해야 하며, 제거공정 자체가 a-Si:H 박막을 부식 하지 않을 조건으로 행하여야 한다. 포토레지스트 제거 후 잔류 포토 레지스트를 제거하기 위해서 본 실험에서는 RCA-I 세척 기법을 사용한 후 D.I 로 린스 하였다. 본 실험에서 사용한 금속은 Cr, Al, ITO 로 모두 DC sputter 방법을 사용해서 증착하여 사용하였다. Cr박막은 $1300\AA$ 정도의 두께를 사용하였고, ITO (Indium Tin Oxide) 박막은 가시광 영역에서 투명하고 (80% 이상의 transmittance), 저저항 (Sheet Resistance : $50{\Omega}/sq$ 이하) 인 박막을 사용하였으며, 신호선으로 주로 사용되는 Al등의 증착조건에 따른 wet etching 특성을 조사하였다.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.37-41
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• 2012

The wafer level stacking with Cu-to-Cu bonding becomes an important technology for high density DRAM stacking, high performance logic stacking, or heterogeneous chip stacking. Cu CMP becomes one of key processes to be developed for optimized Cu bonding process. For the ultra low-k dielectrics used in the advanced logic applications, Ti barrier has been preferred due to its good compatibility with porous ultra low-K dielectrics. But since Ti is electrochemically reactive to Cu CMP slurries, it leads to a new challenge to Cu CMP. In this study Ti barrier/Cu interconnection structure has been investigated for the wafer level 3D integration. Cu CMP wafers have been fabricated by a damascene process and two types of slurry were compared. The slurry selectivity to $SiO_2$ and Ti and removal rate were measured. The effect of metal line width and metal density were evaluated.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.5
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• pp.149-158
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• 2002

Recently, the minimum line width shows a tendency to decrease and the multi-level increases in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. However there are several defects in CMF, such as micro-scratches, abrasive contaminations and non-uniformity of polished wafer edges. Wet etching process including spin-etching can eliminate the defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(Interlayer-Dielectric) was removed by CMP and wet etching process using DHF(Diluted HF) in order to investigate the possibility of planrization by wet etching mechanism. In the thin film wafer, the results were evaluated from the viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And the pattern step heights were also compared for the purpose of planarity characterization of the patterned wafer. Moreover, Chemical polishing process which is the wet etching process with mechanical energy was introduced and evaluated for examining the characteristics of planarization.