• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.57 no.4
• /
• pp.629-634
• /
• 2008

In this paper, we propose a simple numerical formula which can estimate the additional delay time due to interconnection branches in general source-termination scheme. We show that interconnection branches have influence on both signal quality and time delay. Using the proposed numerical formula, time delay can be easily predicted by system designers.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.5 s.335
• /
• pp.39-46
• /
• 2005

This paper introduces a new At-speed Interconnect Test Controller (ASITC) that can detect and diagnose dynamic as well as static defects in an SoC. SoC is comprised of IEEE 1149.1 and P1500 wrapped cores which can be operated by multiple system clocks. In other to test such a complicated SoC, we designed a interface module for P1500 wrapped cores and the ASITC that makes it possible to detect interconnect delay faults during 1 system clock from launching to capturing the transition signal. The ASITC proposed requires less area overhead than other approaches and the operation was verified through the FPGA implementation

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.7
• /
• pp.1-9
• /
• 1999

This paper presents an analytic 3rd order calculation methods, without simulations, for delay time of RC-class circuits which are conveniently used to on-chip interconnects. While the proposed method requires comparable evaluation time than the previous 2nd order calculation method, it ensures more accurate results than those of 2nd order method. The proposed analytic delay calculation method guarantees allowable error tolerances when compared to the results obtained from the AWE (Asymptotic Waveform Evaluation) technique and has better performance in evaluation time as well as numerical stability. The first algorithm of the proposed method requires 8 moments for the 3rd order approximation and yields more accurate delay time approximation. The second algorithm requires 6 moments for the 3rd order approximation and results in shorter evaluation time, the accuracy of which may be less than the first algorithm.

• Journal of Astronomy and Space Sciences
• /
• v.26 no.3
• /
• pp.375-402
• /
• 2009

Korean historical constellations and their names are similar to Chinese ones. Although Korean historical astronomy is influenced by China, they have distinct differences in each shape and names of the constellations. We, therefore, compare Bocheonga (步天歌) of the early Joseon dynasty (朝鮮, $1392{\sim}1910$) preserved in Gyujanggark (奎章閣) with that of the Sui dynasty ((隋代, $581{\sim}618$ of China written by Wang Ximing(王希明) in terms of star charts and descriptions of the contents. We find out that the two books are partly different all over the books. First, there are definite differences in preface, three area of constellations (三垣) in the heaven, and the description of the Milky Way. Second, some of constellations show different in shape, the number of stars. Especially connecting pattern in some constellations shows different in each other. Third, Joseon Bocheonga describes their colors for some stars. These mean that Joseon has a unique tradition of star maps unlike Chinese one. We also summarize the differences and distinctive characteristics of Joseon star charts compared with Chinese ones.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.6
• /
• pp.81-90
• /
• 2004

For deep submicron (DSM) very large scale integrated circuits (VLSI), it is well known that interconnects have become the dominant factor in determining the overall circuit performance. Buffer insertion is an effective technique of interconnect optimization. When a net has an excessive propagation delay, one or more buffers can be inserted to reduce the delay. Buffers also reduce the crosstalk between neighboring wires. While many conventional methods insert buffers net by net. we have developed new techniques in which buffer locations are simultaneously optimized for all nets. This is to avoid the difficulties in finding the right ordering of nets for buffer insertion. since several nets may compete for a buffer location. We also study buffer insertion with multiple fan-out nets to optimize critical path delay. Elmore delay model is used for delay calculation and the number of buffers for each net is determined to optimize the delay.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.9
• /
• pp.19-27
• /
• 2002

Characteristics of interconnect lines considering underlayer geometries of a silicon substrate and crossing metal lines are experimentally analyzed through elaborately devised patterns. In this work, test patterns for transmission lines having several kinds of underlayer geometries were devised, and the signal characteristics and responses are measured by S-parameter and time domain reflection meter (TDR). The patterns were designed and fabricated with a deep-submicron CMOS DRAM technology having 1 Tungsten and 2 Aluminum metals. From the analysis of measured results on the patterns, it is founded that the effects of underlayter line structures on line parameters (especially line capacitance and resistance) and signal distortions occurred from them cannot be negligible. The results provide useful and insightful understanding in the skew balance of package leads and global signal lines such as high-speed clock and data lines.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.4
• /
• pp.549-560
• /
• 1993

A simple closed form approximation is developed by a new approach presented in this paper for the microstrip surface dyadic Green's function which arises in the problem of an electric current point source on an infinite planar grounded dielectric substrate. This closed form approximation includes the effects of the space wave, the surface wave and their coupling within the transition region near the source, and remains accurate as near as $0.1{\pi}_1$ from the source point for a substrate thickness as large as $0.04{\pi}_1$, where, ${\pi}_1$, is the free space wavelength, This result can significantly facilitate the rigorous moment method analysis of microstrip antenna arrays on relatively this substrates of practical interest. Numerical results illustrating the accuracy of the closed form approximation are presented and CPU times associated with some mutual impedance calculations are also included.

• Proceedings of the IEEK Conference
• /
• 2004.06b
• /
• pp.573-576
• /
• 2004

This paper proposes an analytic method that can estimate delay time considering crosstalk noise at an arbitrary node of RC-class interconnects under saturated ramp input using a simple closed-form expression. In the case of single interconnects, algebraic expression presented in existent research can estimate delay time under ramp input using delay time under step input, and we applied it to estimate delay time considering crosstalk noise. As the result, we can provide a intuitive analysis about signal integrity of circuits that include crosstalk noise reducing computational complexity significantly.

• Bulletin of the Society of Naval Architects of Korea
• /
• v.27 no.2
• /
• pp.40-46
• /
• 1990

Expressions for the lift and the drag exerted on a circular cylinder by an unsteady flow of an ideal fluid with embedded discrete vortices are derived. The formulae can be used in the discrete vortex method of flow simulation. These formulae are derived via contour integration on the complex plane. Terms have been produced which are significantly different from those in Sarpkaya's formulae. These are expected to bring a change to the forces obtained so far.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.54 no.7
• /
• pp.299-303
• /
• 2005

This paper proposes an analytic method can estimate delay time considering crosstalk noise at an arbitrary node of RC-class interconnects under saturated ramp input using a simple closed-form expression. In the case of single interconnects, algebraic expression presented in existent research can estimate delay time under ramp input using delay time under step input, and we applied it to estimate delay time considering crosstalk noise. As the result, we can provide a intuitive analysis about signal integrity of circuits that include crosstalk noise reducing computational complexity significantly.