• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.10
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• pp.895-902
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• 2012

In this paper, we propose a novel equalizer to compensate for the group delay including AM/PM nonlinear distortion characteristics by the nonlinear power amplifier (PA). The group delay characteristic is a nonlinear non-constant time delay that appears differently depending on each frequency component. The phase distortion by AM/PM characteristics arising from the power amplifier is a major factor to increase group delay. By the group delay distortion, the signal in the constellation expands and is rotated. Considering the problem mentioned above, the nonlinear time delay that appears differently depending on each frequency component is classified as a static group delay and AM/PM characteristic of PA, the different phase transitions depending on the size of input signal as a dynamic group delay. Static group delay estimates and compensate for phase distortions in the frequency domain with type-based method and dynamic group delay compensates for phase rotation in the time domain. We confirmed that the group delay compensation techniques were enough to compensate the group delay characteristics including AM/PM characteristics of the power amplifier.

• Journal of IKEEE
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• v.19 no.4
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• pp.506-513
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• 2015

In this paper, an output-capacitorless, low-dropout (LDO) regulator is designed, which consumes $4.5{\mu}A$ quiescent current. Proposed LDO regulator is realized using two amplifier for good load regulation and fast response time, which provide high gain, high bandwidth, and high slew rate. In addition, a one-shot current boosting circuit is added for current control to charge and discharge the parasitic capacitance at the pass transistor gate. As a result, response time is improved during load-current transition. The designed circuit is implemented through a $0.11-{\mu}m$ CMOS process. We experimentally verify output voltage fluctuation of 260mV and recovery time of $0.8{\mu}s$ at maximum load current 200mA.

• Journal of the Korea Convergence Society
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• v.7 no.3
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• pp.77-85
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• 2016

We propose a digital signal processing technic that can compensate the non-linearity inherent in audio amplifiers, and present the result of the simulation. The inherent non-linearity of the audio power amplifier arising from analog devices is compensated via a digital signal processing technic consisting of indirect learning architecture and an adaptive filter. The simulation results show that the compensator can be realized using a third-order polynomial and compensates odd-order non-linearity efficiently. The even-oder non-linearity is mainly due to the dc offset at the output, which is difficult to eliminate with the proposed method. Care must be taken in designing the bias circuit to avoid the DC offset at the output. The proposed technic has significance in that digital signal processing technic can compensate for the impairment that is an inherent characteristic of an analog system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.4
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• pp.531-538
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• 1998

In this paper the system performance degradation resulting from nonlinear transmitter power amplifier which is essential to increase the efficiency is analysed in a CDMA system. The power amplifier is modeled by its AM-AM, AM-PM characteristics. The effects of power amplifier's nonlinearity such as intersymbol interference, phase distonion on the RF system performance were visualized by examining the distorted time domain waveforms, signal vector constellation. And through the investigation of the power spectrum density of the transmitted signal, spectral regrowth or sideband regrowth which is result from amplitude distortion can be seen. All these characteristics result in BER performance degradation due to other user interferences and intersymbol interference. The analysis technique described here applies not only to power amplifier but also to any other nonlinear components such as mixers and switches. Also the effects of adjacent channel interference and supurious emission can be analysed between different systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.673-676
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• 2015

Digital Pre-Distortion (DPD) is a linearization technique for nonlinear power amplifiers (PAs) by implementing inverse function of the PA at baseband digital stage. To obtain proper DPD parameters, a feedback path is required to convert the PA output to a baseband signal, and a memory is also needed to store the feedback signals. DPD parameters are usually found by an adaptive algorithm from the feedback samples. However, for the adaptive algorithm to converge to a reliable solution, long feedback samples are required, which increases convergence time and hardware complexity. In this paper, we propose a DPD technique that requires relatively short feedback samples. From the observation that the convergence time of the adaptive algorithm highly depends on the initial condition, this paper iteratively utilizes the feedback samples while keeping and using the converged DPD parameters at the former iteration as the initial condition at the current iteration. Computer simulation results show that the proposed method performs better than the conventional technique while the former requires much shorter feedback samples than the latter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.44-54
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• 2001

In this paper, a novel test method is proposed to detect the hard and soft fault in analog circuits. The proposed test method makes use of the offset voltage, which is one of the op-amps characteristics. During the test mode, CUT is modified to unit gain op-amps with feedback loop. When the input of the op-amp is grounded, a good circuit has a small offset voltage, but a faulty circuit has a large offset voltage. Faults in the op-amp which cause the offset voltage exceeding predefined range of tolerance can be detected. In the proposed method, no test vector is required to be applied. Therefore the test vector generation problem is eliminated and the test time and cost is reduced. In this note, the validity of the proposed test method has been verified through the example of the dual slope A/D converter. The HSPICE simulations results affirm that the presented method assures a high fault coverage.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.9
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• pp.6247-6253
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• 2015

This paper presents the transient-response improved LDO regulator based on parallel error amplifiers. The proposed LDO regulator consists of an error amplifier (E/A1) which has a high gain and narrow bandwidth and a second amplifier (E/A2) which has low gain and wide bandwidth. These amplifiers are in parallel structure. Also, to improve the transient-response properties and slew-rate, some circuit block is added. Using pole-splitting technique, an external capacitor is reduced in a small on-chip size which is suitable for mobile devices. The proposed LDO has been designed and simulated using a Megna/Hynix $0.18{\mu}m$ CMOS parameters. Chip layout size is $500{\mu}m{\times}150{\mu}m$. Simulation results show 2.5 V output voltage and 100 mA load current in an input condition of 2.7 V ~ 3.3 V. Regulation Characteristic presents voltage variation of 26.1 mV and settling time of 510 ns from 100mA to 0 mA. Also, the proposed circuit has been shown voltage variation of 42.8 mV and settling time of 408 ns from 0 mA to 100 mA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.100-105
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• 2003

In this paper, we propose the novel test method effectively to detect short and open faults in CMOS op-amp. The proposed method uses a sinusoidal signal with higher frequency than unit gain bandwidth. Since the proposed test method doesn't need complex algorithm to generate test pattern, the time of test pattern generation is short, and test cost is reduced because a single test pattern is able to detect all target faults. To verify the proposed method, CMOS two-stage operational amplifier with short and open faults is designed and the simulation results of HSPICE for the circuit have shown that the proposed test method can detect short and open faults in CMOS op-amp.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.17-26
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• 2003

To reduce the nonlinear distortion of high power amplifier(HPA) in down link OFCDM system to employ time domain spreading, we apply technology which transmits MPSK(Multilevel-PSK) signal after clipping on multilevel input signal of IFFT subcarrier. In case that the nonlinear distortion of HPA is considered in AWGN channel, performacne of clipping OFCDM system using extended m sequence is over 2.2㏈ better than that of OFCDM system using extended m sequence when the number of user is 8 and 16. In case that the nonlinear distortion of HPA is considered in quasi-static channel, performacne of clipping OFCDM system using extended m code is over 2㏈ better than that of OFCDM system using extended m sequence when the number of user is 8 and 16.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.9-15
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• 2009

In this paper, we invented a new structure of fast ATC(Automatic Threshold Control) circuit. Using the structure we made a new burst-mode limiting amplifier with fast ATC function using commercial $0.8{\mu}m$ BiCMOS technology. It's ATC function worked so fast that even the first bit of burst-data could be detected, which confirmed that the new structure was useful for fast ATC. However, in the beginning of a burst, distortions in duty-cycle occurred and increased up to 59% of duty-cycle as amplitude of input signal increased. But we confirmed that after 10 cycles passed, duty-cycles was staying below 52% of duty-cycle for any magnitude of input signal.