• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1017-1020
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• 1998

We propose an algorithm which processes the floating-point $n_{addition}$traction and rounding in parallel. It also processes multiplication and rounding in the same way. The hardware model is presented that minimizes the delay time to get results for all the rounding modes defined in the IEEE Standards. An unified method to get the three bits(L, G, S)for the rounding is described. We also propose an unified guide line to determine the 1-bit shift for the post-normalization in the Floating-point $n_{addition}$traction and multiplication.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1997.10a
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• pp.402-408
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• 1997

일정 학습계수와 이진 강화함수를 지닌 자기조직화 형상지도(Self-Organizing Feature Map)신경회로망을 FPGA위에 하드웨어로 구현하였다. 원래의 SOFM 알고리즘에서 학습계수가 시간 종속형인데 반하여, 본 논문에서 하드웨어로 구현한 알고리즘에서는 학습계수가 일정인 값으로 고정되며 이로 인한 성능저하를 보상하기 위하여 이진 강화함수를 부가하였다. 제안한 알고리즘은 복잡한 곱셈 연산을 필요로 하지 않으므로 하드웨어 구현시 보다 쉽게 구현 가능한 특징이 있다. 1개의 덧셈/뺄셈기와 2개의 덧셈기로 구성된 단위 뉴런은 형대가 단순하면서 반복적이므로 하나의 FPGA위에서도 다수의 뉴런을 구현 할 수 있으며 비교적 소수의 제어 신호로서 이들을 모두 제어 가능할 수 있도록 설계하였다. 실험결과 각 구성부분은 모두 이상 없이 올바로 동작하였으며 각 부분이 모두 종합된 전체 시스템도 이상 없이 동작함을 알 수 있었다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.3
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• pp.511-514
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• 2019

Elliptic Curves Cryptosystem(ECC) provides the same level of security with relatively small key sizes, as compared to the traditional cryptosystems. The performance of ECC over GF(2m) and GF(p) depends on the efficiency of finite field arithmetic, especially the modular multiplication which is based on the reduction algorithm. In this paper, we propose a new modular reduction algorithm which provides high-speed ECC over NIST prime P-256. Detailed experimental results show that the proposed algorithm is about 25% faster than the previous methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3C
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• pp.176-184
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• 2005

In this paper, we implemented an Elliptic Curve Cryptography(ECC) processor for Digital Transmission Contents Protection (DTCP), which is a standard for protecting various digital contents in the network. Unlikely to other applications, DTCP uses ECC algorithm which is defined over GF(p), where p is a 160-bit prime integer. The core arithmetic operation of ECC is a scalar multiplication, and it involves large amount of very long integer modular multiplications and additions. In this paper, the modular multiplier was designed using the well-known Montgomery algorithm which was implemented with CSA(Carry-save Adder) and 4-level CLA(Carry-lookahead Adder). Our new ECC processor has been synthesized using Samsung 0.18 m CMOS standard cell library, and the maximum operation frequency was estimated 98 MHz, with the size about 65,000 gates. The resulting performance was 29.6 kbps, that is, it took 5.4 msec to process a 160-bit data frame. We assure that this performance is enough to be used for digital signature, encryption and decryption, and key exchanges in real time environments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.3
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• pp.419-426
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• 2021

A high-performance elliptic curve cryptography processor (HP-ECCP) was designed to support five field sizes of 192, 224, 256, 384 and 521 bits over GF(p) defined in NIST FIPS 186-2, and it provides eight modes of arithmetic operations including ECPSM, ECPA, ECPD, MA, MS, MM, MI and MD. In order to make the HP-ECCP resistant to side-channel attacks, a modified left-to-right binary algorithm was used, in which point addition and point doubling operations are uniformly performed regardless of the Hamming weight of private key used for ECPSM. In addition, Karatsuba-Ofman multiplication algorithm (KOMA), Lazy reduction and Nikhilam division algorithms were adopted for designing high-performance modular multiplier that is the core arithmetic block for elliptic curve point operations. The HP-ECCP synthesized using a 180-nm CMOS cell library occupied 620,846 gate equivalents with a clock frequency of 67 MHz, and it was evaluated that an ECPSM with a field size of 256 bits can be computed 2,200 times per second.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.66-73
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• 2002

As floating-point operations become widely used in various applications such as computer graphics and high-definition DSP, the needs for fast division become increased. However, conventional floating-point dividers occupy a large hardware area, and bring bottle-becks to the entire floating-point operations. In this paper, a high-performance and small-area floating-point divider, which is suitable for embedded processors, is designed using he series expansion algorithm. The algorithm is selected to utilize two MAC(Multiply-ACcumulate) units for quadratic convergence to the correct quotient. The two MAC units for SIMD-DSP features are shared and the additional area for the division only is very small. The proposed divider supports all rounding modes defined by IEEE 754 standard, and error estimations are performed for appropriate precision.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.6
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• pp.17-28
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• 2002

XTR is a new method to represent elements of a subgroup of a multiplicative group of a finite field GF( $p^{6m}$) and it can be generalized to the field GF( $p^{6m}$)$^{[6,9]}$ This paper progress optimal extention fields for XTR among Galois fields GF ( $p^{6m}$) which can be aplied to XTR. In order to select such fields, we introduce a new notion of Generalized Opitimal Extention Fields(GOEFs) and suggest a condition of prime p, a defining polynomial of GF( $p^{2m}$) and a fast method of multiplication in GF( $p^{2m}$) to achieve fast finite field arithmetic in GF( $p^{2m}$). From our implementation results, GF( $p^{36}$ )longrightarrowGF( $p^{12}$ ) is the most efficient extension fields for XTR and computing Tr( $g^{n}$ ) given Tr(g) in GF( $p^{12}$ ) is on average more than twice faster than that of the XTR system on Pentium III/700MHz which has 32-bit architecture.$^{［6,10］/ ［6,10］/6,10］}$

• The KIPS Transactions:PartC
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• v.18C no.1
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• pp.1-6
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• 2011

The performance and practicality of cryptosystem for encryption, decryption, and primality test is primarily determined by the implementation efficiency of the modular exponentiation of $a^b$(mod n). To compute $a^b$(mod n), the standard binary squaring still seems to be the best choice. But, the d-ary, (d=2,3,4,5,6) method is more efficient in large b bits. This paper suggests m-numeral system modular exponentiation. This method can be apply to$b{\equiv}0$(mod m), $2{\leq}m{\leq}16$. And, also suggests the another method that is exit the algorithm in the case of the result is 1 or a.

• 한국HCI학회:학술대회논문집
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• 2008.02a
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• pp.403-408
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• 2008

본 논문은 모바일 그래픽스 응용에 적합한 메쉬 위치정보의 압축 기법을 제시한다. 제시한 기법은 복원 에러를 최소화하기 위한 메쉬 분할 기법과 기존의 방법에서 방생하는 시각적 손상문제를 해결한 지역적 정량화 기법으로 구성된다. 기존 방법에서는 분할된 조각 메쉬들 간의 경계가 벌어지는 시각적 손상문제가 방생하는데, 모든 조각 메쉬의 지역적 양자화 셀이 같은 크기와 정렬된 지역 좌표축을 갖게 하여 이 문제를 해결했다. 제시한 기법은 메쉬를 렌더링할 때 압축된 위치정보를 메모리에서 그래픽스 하드웨어로 전송하여 실시간으로 복원함으로써 모바일 기기의 자원을 절약하는 특징을 갖는다. 압축된 위치정보의 복원을 표준화된 렌더링 파이프라인에 결합이 가능하도록 설계함으로써 조각 메쉬당 한번의 행렬 곱셈으로 복원이 가능하다. 실험에서는 32 비트 부동소수점 수로 표현되는 위치정보를 8 비트 정수로 지역적 정량화하여 70%의 압축률에서 11 비트 전역적 정량화와 대등한 수준의 시각적 품질을 달성했다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.163-165
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• 2018

GF(p)상 타원곡선 암호(ECC)와 RSA를 단일 하드웨어로 통합하여 구현한 공개키 암호 프로세서를 설계하였다. 설계된 EC-RSA 공개키 암호 프로세서는 NIST 표준에 정의된 소수체 상의 224-비트 타원 곡선 P-224와 2048-비트 키 길이의 RSA를 지원한다. ECC와 RSA가 갖는 연산의 공통점을 기반으로 워드기반 몽고메리 곱셈기와 메모리 블록을 효율적으로 결합하여 최적화된 데이터 패스 구조를 적용하였다. EC-RSA 공개키 암호 프로세서는 Modelsim을 이용한 기능검증을 통하여 정상동작을 확인하였으며, $0.18{\mu}m$ CMOS 셀 라이브러리로 합성한 결과 11,779 GEs와 14-Kbit RAM의 경량 하드웨어로 구현되었다. EC-RSA 공개키 암호 프로세서는 최대 동작주파수 133 MHz이며, ECC 연산에는 867,746 클록주기가 소요되며, RSA 복호화 연산에는 26,149,013 클록주기가 소요된다.