Study on Parallelized Rounding Algorithm in Floating-point Addition and Multiplication

부동소수점 덧셈과 곱셈에서의 라운딩 병렬화 알고리즘 연구

We propose an algorithm which processes the floating-point $n_{addition}$traction and rounding in parallel. It also processes multiplication and rounding in the same way. The hardware model is presented that minimizes the delay time to get results for all the rounding modes defined in the IEEE Standards. An unified method to get the three bits(L, G, S)for the rounding is described. We also propose an unified guide line to determine the 1-bit shift for the post-normalization in the Floating-point $n_{addition}$traction and multiplication.