• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.7
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• pp.1657-1662
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• 2014

In this paper, the impact of substrate bias($V_{BS}$) on the zero capacitor RAM(Z-RAM) in n-channel junctionless multiple gate MOSFET(MuGFET) has been analyzed experimentally. Junctionless transistors with fin width of 50nm and 1 fin exhibits a memory window of 0.34V and a sensing margin of $1.8{\times}10^4$ at $V_{DS}=3.5V$ and $V_{BS}=0V$. As the positive $V_{BS}$ is applied, the memory window and sensing margin were improved due to an increase of impact ionization. When $V_{BS}$ is increased from 0V to 10V, not only the memory window is increased from 0.34V to 0.96V but also sensing margin is increased slightly. The sensitivity of memory window with different $V_{BS}$ in junctionless transistor was larger than that of inversion-mode transistor. A retention time of junctionless transistor is better than that of inversion-mode transistor due to low Gate Induced Drain Leakage(GIDL) current. To evaluate the device reliability of Z-RAM, the shifts in the Set/Reset voltages and current were measured.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.04a
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• pp.986-988
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• 2012

최적의 식물 생장을 위해서는 적절한 수분의 유지가 필수적이며 넓은 지역, 다양한 종류, 고가의 식물의 경우일수록 적절한 수분의 관리를 위한 시스템의 도움이 필요하다. 이를 위해 저가의 센서노드 시스템이 적절한 해결책이 될 수 있으나 일반적인 배터리 기반의 센서노드 시스템을 적용시 배터리 용량 확인 및 교체 등의 유지보수 문제가 대두된다. 본 논문에서는 이러한 유지보수의 문제를 해결하고 식물재배에 도움을 줄 수 있는 자기유지 지원 방식의 정전용량 센싱기반의 수분 모니터링 센서노드를 설계하였다. UHF 기반의 무선 전력 전송의 자기유지 지원 시스템 및 PCB 패턴기반의 정전용량센싱 수분센서와 초저전력 센서노드 시스템으로 구성된다. 센서노드는 한번 송신시 약 0.24 mJ을 소모하며 에너지획득모듈은 에너지 획득 주기마다 약 4 mJ의 에너지를 공급하도록 설계하여 센서동작을 위한 충분한 에너지 마진을 주도록 설계하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.722-725
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• 2012

In this paper, we design an 8-bit eSuse OTP (one-time programmable) memory based on a $0.35{\mu}m$ BCD process using differential paired eFuse cells which can sense BL data without a reference voltage and also have smaller sensing resistances of programmed eFuse links. The channel widths of a program transistor of the differential eFuse OTP cell are splitted into $45{\mu}m$ and $120{\mu}m$. Also, we implement a sensing margin test circuit with variable pull-up loads in consideration of variations of the programmed eFuse resistances. It is confirmed by measurement results that the designed 8-bit eFuse OTP memory IP gives a better yield when the channel width is $120{\mu}m$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.405-413
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• 2013

In this paper, a high-reliability differential paired 24-bit eFuse OTP memory with program-verify-read mode for PMICs is designed. In the proposed program-verify-read mode, the eFuse OTP memory can do a sensing margin test with a variable pull-up load in consideration of programmed eFuse resistance variation and can output a comparison result through a PFb (pass fail bar) pin by comparing a programmed datum with its read one. It is verified by simulation results that the sensing resistance is lower with $4k{\Omega}$ in case of the designed differential paired eFuse OTP memory than $50k{\Omega}$ in case of its dual-port eFuse OTP memory.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.7
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• pp.1455-1462
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• 2012

In this paper, a BCD process based high-reliability 24-bit dual-port eFuse OTP Memory for PMICs is designed. We propose a comparison circuit at program-verify-read mode to test that the program datum is correct by using a dynamic pseudo NMOS logic circuit. The comparison result of the program datum with its read datum is outputted to PFb (pass fail bar) pin. Thus, the normal operation of the designed OTP memory can be verified easily by checking the PFb pin. Also we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse at program-verify-read mode. We design a 24-bit eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $289.9{\mu}m{\times}163.65{\mu}m$ ($=0.0475mm^2$).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2359-2368
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• 2013

In this paper, an IRD (internal read data) circuit preventing the reentry into the read mode while keeping the read-out DOUT datum at power-up even if noise such as glitches occurs at signal ports such as an input signal port RD (read) when a power IC is on, is proposed. Also, a pulsed WL (word line) driving method is used to prevent a DC current of several tens of micro amperes from flowing into the read transistor of a differential paired eFuse OTP cell. Thus, reliability is secured by preventing non-blown eFuse links from being blown by the EM (electro-migration). Furthermore, a compared output between a programmed datum and a read-out datum is outputted to the PFb (pass fail bar) pin while performing a sensing margin test with a variable pull-up load in consideration of resistance variation of a programmed eFuse in the program-verify-read mode. The layout size of the 8-bit eFuse OTP IP with a $0.18{\mu}m$ process is $189.625{\mu}m{\times}138.850{\mu}m(=0.0263mm^2)$.