• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.2
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• pp.141-146
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• 2016

This paper presents a method to improve time interval error for asynchronous communication systems. The proposed method is designed and simulated with multi-phase VCO, interpolator, phase selector, up-down counter, comparator and adder. The simulation results for CAN communication system show that the maximum time interval error can be tightly managed for satisfying the required specification. The proposed frequency modulation method can be properly used for asynchronous communication systems requiring high reliability.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.59-65
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• 2013

Conventional synchronous design circuits cannot only satisfy the timing requirement of the low voltage digital systems, but also they may generate wrong outputs under the influence of PVT variations and aging effects. Therefore, in this paper, a NCL (Null Convention Logic) design as an asynchronous design method has been proposed, where the NCL method doesn't require any timing analysis, and it has a very simple design methodology. Base on the NCL method, a new low power reliable ALU has been designed and implemented using MagnaChip-SKhynix 0.18um CMOS technology. The experimental results of the proposed NCL ALU have been compared to those of a conventional pipelined ALU in terms of power consumption and speed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.9
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• pp.47-54
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• 2000

We designed asynchronous event logic library with 0.25um CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6GHz. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A Method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about $1.1mm{\times}1.1mm$.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.49-58
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• 2016

In designing heterogeneous architecture based application-specific network-on-chips (NoCs), the opportunities of performance improvement would be expanded when applying asynchronous on-chip communication protocol. This is because the wire latency can be configured independently considering the wirelength of each link. In this paper, we develop the delay model of link-wire-length in asynchronous NoC and propose simulated annealing (SA) based floorplan-aware topology generation algorithm to optimize link-wirelengths. Incorporating the generated topology and the associated latency values across all links, we evaluate the performance using the floorplan-annotated sdf (standard delay format) file and RTL-synthesized gate-level netlist. Compared to TopGen, one of general topology generation algorithms, the experimental results show the reduction in latency by 13.7% and in execution time by 11.8% in average with regards to four applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.429-438
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• 2004

In this paper, a decision-feedback coherent code tracking loop is designed for WCDMA systems and its performance is analyzed in terms of jitter variance considering the effect of phase and symbol estimation errors for both AWGN and fading environments. An analytical closed-form formula for jitter variance is Int derived for AWGN environments as a function of a pulse-shaping filter, timing offset, signal-to-interference ratio, and loop bandwidth while involving the phase estimation error and bit error rate, and the upper bound of jitter variance is derived for fading environments. Finally a second-order coherent code tracking loop is designed with the DPCH frame format #13 of the WCDHA forward link selected as a target system, and its performance is evaluated by the closed-form formula and compared with the simulation results for both AWGN and Rayleigh fading environments.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.165-166
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• 2013

기존의 위상천이 풀 브리지 DC/DC 컨버터의 경우 변압기의 누설 인덕턴스와 정류 스위치의 기생 출력 캐패시턴스 사이의 공진으로 인하여 정류 스위치에 스파이크 전압이 발생하며, 이는 시스템의 전력 변환 효율을 감소시킨다. 최근에 보조 DC/DC 컨버터를 사용하여 클램핑 캐패시터에서 흡수된 에너지를 부하로 회기시키는 방법이 연구되고 있으나, 보조 DC/DC 컨버터를 설계하기 위한 정확한 분석은 제시되지 않았다. 따라서, 본 논문에서는 2차 측 정류기의 공진 전압을 저감할 수 있는 비동기식 능동형 스너버 회로의 설계방법을 제안한다. 또한, 초기 기동 시에 발생되는 큰 공진에너지를 히스테리시스 회로를 이용하여 저항을 통해 소모시킴으로써 보조 DC/DC 컨버터의 자성소자를 최소화할 수 있다. 본 논문에서는 제안된 방식의 타당성을 검증하기 위하여 이론적으로 분석하며, 450W급 시작품을 제작하여 제안방식의 타당성을 검증하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.36-44
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• 2007

This paper presented a hybrid ternary encoding scheme using 3-valued logic. It can adapt to the delay-insensitive(DI) model. We designed an asynchronous wrapper for the hybrid ternary encoding scheme to communicate with various asynchronous encoding schemes. It reduced about 50% of transmission lines and power consumption compared with the conventional 1-of-4 and ternary encoding scheme. The proposed wrappers were designed and simulated using the $0.18-{\mu}m$ standard CMOS technology. As a result, the asynchronous wrapper operated over 2 GHz communicating with a system bus. Moreover, the power dissipation of the system bus adapted the hybrid ternary encoding logic decreases 65%, 43%, and 36% of the dual-rail, 1-of-4, and ternary encoding scheme, respectively. The proposed data encoding scheme and the wrapper circuit can be useful for asynchronous high-speed and low-power asynchronous interface.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.1
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• pp.1-9
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• 1987

In this paper, the acquisition performance of a receiver that utilizes a non-coherent digital correlator is analyzed. In order to analyze the acquisition performance, the probability density function of a receiver output random variable has been derived approximately. Using this function, the acquisition performance of the coarse acquisition code receiver in a global positioning system is analyzed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.1
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• pp.209-219
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• 2011

Most of the computer-based distance learning systems are asynchronous ones that allow students to download from the server the lecture previously given by a lecturer. While these asynchronous systems has the advantage that enable students to view the lecture with no time restriction, the study may not be effective due to the lack of support for real-time interaction between students and lecturers. Based on the student-lecturer-collaboration session model, this paper presents a collaboration session-centric synchronous distance learning system that supports real-time interaction between students and teachers, awareness information during lecture, and feedback from students. Basic feature of the proposed system include audio and video conferencing, text-based chat, and shared slide with annotation support.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.321-334
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• 2003

Globally-Asynchronous Locally-Synchronous (GALS) systems are worthy of notice as an adequate architecture for a large scaled chip design with guaranteeing easy designs and functional confidence. In this paper, we suggest an advanced structure of the interface unit which is indispensable for GALS systems by using stoppable clocks. The proposed interface unit is composed of a sender module and a receiver module. The sender module can carry out data transmission partially without the relation to an internal clock. We have designed it with 0.25${\mu}{\textrm}{m}$ standard cell library at the gate level and simulated its operation to show performance improvement. Finally, we constructed all example circuit with the interface unit and proved the correct operation of it.