• The Transactions of the Korea Information Processing Society
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• v.7 no.10
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• pp.3290-3299
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• 2000

Digital watermarking has similar concepts with channel coding thechnique for transferring data with minimizing error in noise environment, since it should be robust to various kinds of data manipulation for protecting copyrights of multimedia data. This paper proposes a digital watermarking technique which is robust to various kinds of data manipulation. Intellectual property rights information is encoded using a convolutional code, and block-interleaving technique is applied to prevent successive loss of encoded data. Encoded intelloctual property rithts informationis embedded using spread spectrum technique which is robust to cata manipulation. In order to reconstruct intellectual property rights information, watermark signalis detected by covariance between watermarked image and pseudo rando noise sequence which is used to einbed watermark. Embedded intellectual property rights information is obtaned by de-interleaving and cecoding previously detected wtermark signal. Experimental results show that block interleaving watermarking technique can detect embedded intellectial property right informationmore correctly against to attacks like Gaussian noise additon, filtering, and JPEG compression than general spread spectrum technique in the same PSNR.

• Journal of Korea Multimedia Society
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• v.10 no.1
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• pp.58-65
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• 2007

This dissertation proposes digital video protection algorithm lot moving image based on MPEG. Shuffling-based encryption algorithms using a fixed random shuffling table are quite simple and effective but vulnerable to the chosen plaintext attack. To overcome this problem, it is necessary to change the key used for generation of the shuffling table. However, this may pose a significant burden on the security key management system. A better approach is to generate the shuffling table based on the local feature of an image. In order to withstand the chosen plaintext attack, at first, we propose a interleaving algorithm that is adaptive to the local feature of an image. Secondly, using the multiple shuffling method which is combined interleaving with existing random shuffling method, we encrypted the DPCM processed 8*8 blocks. Experimental results showed that the proposed algorithm needs only 10% time of SEED encryption algorithm and moreover there is no overhead bit. In video sequence encryption, multiple random shuffling algorithms are used to encrypt the DC and AC coefficients of intra frame, and motion vector encryption and macroblock shuffling are used to encrypt the intra-coded macroblock in predicted frame.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10e
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• pp.481-483
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• 2002

압축한 비디오데이타를 네트워크으로 전송 시 채널이 불안정한 경우 패킷이 분실될 우려가 있다. 패킷 분실은 대부분 버스트오류로 나타난다. 본 연구에서는 디코더에서 버스트오류를 효과적으로 은닉, 처리하는 방법으로 오류 내성 비디오 인코딩 방법을 제안한다. 이를 위해 공간적 오류은닉법으로 오류 패킷 분실을 야기시키는 손실 블록을 분리하는데 효과적인 블록 인터리빙을 적용한다. 시간적 오류 은닉에 대해서는 연속적인 내부프레임 또는 프레임간에 움직임벡터의 프레임간 패리티 비트를 삽입하는 구조를 적용한다. 비디오 인코딩 단계를 거쳐 디코더에서 수신한 블록들에 대해서는 쌍선형 보간법을 적용하여 전송시 발생한 국지적 오류를 적절하게 은닉 처리한다. 본 논문에서 제안한 인코딩 방법을 전송 블록에 부가 데이터로 포함하는 것은 표준 엔코더의 복잡도에 거의 영향을 미치지 않는다.

• Journal of IKEEE
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• v.19 no.2
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• pp.168-175
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• 2015

In this paper, we propose FPGA design technique for rotating LED display device which is capable of displaying videos with the use of the afterimage effect. The proposed technique is made up of image data correction process based on inverse gamma correction and error diffusion, block interleaving process, and data serial output process. The data correction process based on inverse gamma correction and error diffusion is an image data correction step in which image data received are corrected by inverse gamma correction process to convert the data into linear brightness characteristics, and by error diffusion process to reduce the brightness reduction phenomenon in low-gray-level which is caused by inverse gamma correction. In the block interleaving process, the data of the frames entered transversely are first saved in accordance with entrance order, and then only the longitudinal image data are read. The data serial output process is applied to convert the parallel data in a rotating location into serial data and send them to LED Driver IC, in order to send data which will be displayed on high-speedy rotating LED Bar. To evaluate the accuracy of the proposed FPGA design technique, this paper used XC6SLX45-FG484, a Spartan 6 family of Xilinx, as FPGA, and ISE 14.5 as a design tool. According to the evaluation analysis, it was found that goal values were consistent with simulation values in terms of accurate operation of inverse gamma and error diffusion correction, block interleaving operation, and serialized operation of image data.

• The KIPS Transactions:PartB
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• v.10B no.2
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• pp.143-150
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• 2003

Error concealment plays an important role in combating transmission errors. Methods of error concealment which produce better quality are generally of higher complexity, thus making some of the more sophisticated algorithms is not suitable for real-time applications. In this paper, we develop temporal and spatial error resilient video encoding and data hiding approach to facilitate the error concealment at the decoder. Block interleaving scheme is introduced to isolate erroneous blocks caused by packet losses for spatial area of error resilience. For temporal area of error resilience, data hiding is applied to the transmission of parity bits to protect motion vectors. To do error concealment quickly, a set of edge features extracted from a block is embedded imperceptibly using data hiding into the host media and transmitted to decoder. If some part of the media data is damaged during transmission, the embedded features are used for concealment of lost data at decoder. This method decreases a complexity of error concealment by reducing the estimation process of lost data from neighbor blocks. The proposed data hiding method of parity bits and block features is not influence much to the complexity of standard encoder. Experimental results show that proposed method conceals properly and effectively burst errors occurred on transmission channel like Internet.

• Journal of the Korea Society for Simulation
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• v.17 no.1
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• pp.17-22
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• 2008

Double-binary turbo code has been adopted as an error control code of various future communication systems including wireless metropolitan area networks(WMAN) due to its powerful error correction capability. One of the components affecting the performance of turbo code is internal interleaver. In 802.16 d/e system, an almost regular permutation(ARP) interleaver has been included as a part of specification, however it seems that the interleaver is not optimized in terms of decoding performance. In this paper, we propose three optimization methods for the interleaver based on spatial distance, spread and minimum distance between original and interleaved sequence. We find optimized interleaving parameters for each optimization method and evaluate the performances of the proposed methods by computer simulation under additive white Gaussian noise(AWGN) channel. Optimized parameters can provide up to 1.0 dB power gain over the conventional method and furthermore the obtainable gain does not require any additional hardware complexity.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.788-791
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• 2005

In this paper, We propose performance of improvement method for eHDR-WPAN system using Interleaver. Burst error pattern caused by fading in indoor wireless channel. for the reason, using of Interleave method (make burst error to random error) can be enhance to error-rate in system. This paper is used Convolutional, Block, Random Interleaver. We make use of 9 and 27 for symbol spacing. Block-Interleaver is show that performance about 0.6dB of E$_b$/N$_o$ at $10^{-4}$. In result, the suitable Interleaver for eHDR-WPAN system is Block Interleaver of 9 symbol spacing.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.3
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• pp.40-49
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• 1989

A variable-state block interference channel model is presented which matches asynchronous multiple-access slow frequency-hopped spread-spectrum systems which suffer from bursts of interference of variable duration. For variable-state block interference channels test pattern techniques combined with interleaving are presented from which the decoder obtain side information about channel states. By examining test patterns the decoder estimates which parts of data blocks are affected by interference and regards the parts of blocks affected by interference as erasures. Since the presence of test patterns reduces the number of bits for data transmission, test patterns are not useful for variable-state block interference channels for small hit probability, It is shown that test patterns increase the capacities of variable-state block interference channels for large hit probability. It is also shown that test patterns provide a almost full side information about channel states for certain values of parameters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.11
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• pp.1502-1506
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• 2016

HEVC (High Efficiency Video Coding) is a recently proposed video compression standard that has a two times greater coding efficiency than previous video compression standards. The key factors of high compression performance and increasement of computational complexity are the various types of block partitions and modes of intra prediction in HEVC. This paper presents an intra prediction hardware architecture for HEVC utilizing pipelining and interleaving techniques to increase the efficiency and performance while reducing the requirement for hardware resources.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.63-72
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• 2012

In this paper, we proposed a parallel architecture of line & block edge filter for high-performance H.264/AVC deblocking filter for Quad Full High Definition(Quad FHD) video real time processing. To improve throughput, we designed 4-parallel block edge filter with 16 line edge filter. To reduce internal buffer size and processing cycle, we scheduled 4-parallel zig-zag scan order as deblocking filtering order. To avoid data conflicts we placed 1 delay cycle between block edge filtering. We implemented interleaving buffer, as internal buffer of block edge filter, to sharing buffer for reducing buffer size. The proposed architecture was simulated in 0.18um standard cell library. The maximum operation frequency is 108MHz. The gate count is 140.16Kgates. The proposed H.264/AVC deblocking filter can support Quad FHD at 113.17 frames per second by running at 90MHz.