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A 4-parallel Scheduling Architecture for High-performance H.264/AVC Deblocking Filter  

Ko, Byung-Soo (Department of Computer Engineering, Kwangwoon University)
Kong, Jin-Hyeung (Department of Computer Engineering, Kwangwoon University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.49, no.8, 2012 , pp. 63-72 More about this Journal
Abstract
In this paper, we proposed a parallel architecture of line & block edge filter for high-performance H.264/AVC deblocking filter for Quad Full High Definition(Quad FHD) video real time processing. To improve throughput, we designed 4-parallel block edge filter with 16 line edge filter. To reduce internal buffer size and processing cycle, we scheduled 4-parallel zig-zag scan order as deblocking filtering order. To avoid data conflicts we placed 1 delay cycle between block edge filtering. We implemented interleaving buffer, as internal buffer of block edge filter, to sharing buffer for reducing buffer size. The proposed architecture was simulated in 0.18um standard cell library. The maximum operation frequency is 108MHz. The gate count is 140.16Kgates. The proposed H.264/AVC deblocking filter can support Quad FHD at 113.17 frames per second by running at 90MHz.
Keywords
H.264/AVC; deblocking filter; block & edge filter; parallel architecture; zig-zag scan order;
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