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http://dx.doi.org/10.7840/kics.2016.41.11.1502

High-Speed Intra Prediction VLSI Implementation for HEVC  

Jo, Hyeonsu (Dongguk University Department of Electronic & Electrical Engineering)
Hong, Youpyo (Dongguk University Department of Electronic & Electrical Engineering)
Jang, Hanbeyoul (Dongguk University Department of Electronic & Electrical Engineering)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.41, no.11, 2016 , pp. 1502-1506 More about this Journal
Abstract
HEVC (High Efficiency Video Coding) is a recently proposed video compression standard that has a two times greater coding efficiency than previous video compression standards. The key factors of high compression performance and increasement of computational complexity are the various types of block partitions and modes of intra prediction in HEVC. This paper presents an intra prediction hardware architecture for HEVC utilizing pipelining and interleaving techniques to increase the efficiency and performance while reducing the requirement for hardware resources.
Keywords
HEVC; Intra prediction; Hardware; Architecture; VLSI; Pipeline;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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