• Management & Information Systems Review
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• v.39 no.2
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• pp.39-60
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• 2020

Block chain technology is one of the core elements for realizing the 4^th industrial revolution, and many efforts have been made by government and companies to provide services based on block chain technology. In this study we analyzed the benefits of block chain technology for EVMS and designed EVMS block chain platform with increased data security and work efficiency for project management data, which are important assets in monitoring progress, foreseeing future events, and managing post-completion. We did the case studies on the benefits of block chain technology and then conducted the survey study on security, reliability, and efficiency of block chain technology, targeting 18 block chain experts and project developers. And then, we interviewed EVMS system operator on the compatibility between block chain technology and EVM Systems. The result of the case studies showed that block chain technology can be applied to financial, logistic, medical, and public services to simplify the insurance claim process and to improve reliability by distributing transaction data storage and applying security·encryption features. Also, our research on the characteristics and necessity of block chain technology in EVMS revealed the improvability of security, reliability, and efficiency of management and distribution of EVMS data. Finally, we designed a network model, a block structure, and a consensus algorithm model and combined them to construct a conceptual block chain model for EVM system. This study has the following contribution. First, we reviewed that the block chain technology is suitable for application in the defense sector and proposed a conceptual model. Second, the effect that can be obtained by applying block chain technology to EVMS was derived, and the possibility of improving the existing business process was derived.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.100-108
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• 2018

This paper describes a design of scalable RSA public-key cryptography processor supporting four key lengths of 512/1,024/2,048/3,072 bits. The modular multiplier that is a core arithmetic block for RSA crypto-system was designed with 32-bit datapath, which is based on the CIOS (Coarsely Integrated Operand Scanning) Montgomery modular multiplication algorithm. The modular exponentiation was implemented by using L-R binary exponentiation algorithm. The scalable RSA crypto-processor was verified by FPGA implementation using Virtex-5 device, and it takes 456,051/3,496347/26,011,947/88,112,770 clock cycles for RSA computation for the key lengths of 512/1,024/2,048/3,072 bits. The RSA crypto-processor synthesized with a $0.18{\mu}m$ CMOS cell library occupies 10,672 gate equivalent (GE) and a memory bank of $6{\times}3,072$ bits. The estimated maximum clock frequency is 147 MHz, and the RSA decryption takes 3.1/23.8/177/599.4 msec for key lengths of 512/1,024/2,048/3,072 bits.

• Journal of IKEEE
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• v.22 no.1
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• pp.104-109
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• 2018

This paper presents a hardware design for the block encryption algorithm of ARIA which is used for standard in Korea. It presents a hardware-efficient design to increase the throughput for the ARIA algorithm using a high-speed pipeline architecture. We have used ROM for the S-box implementation. This approach aims to decrease the critical path delay of the encryption. In this paper, hardware was designed by VHDL, realized RTL level by Synplify which is synthesis tool and verified simulation by ModelSim. The ARIA algorithm is shown 68.3 MHz (Maximum operation frequency) to use Xilinx VertxE XCV Series device.

• Journal of the Korea Convergence Society
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• v.10 no.1
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• pp.25-33
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• 2019

The security of the data dealt by the smart city system is important because they have many privacy and public information. Therefore, it is necessary to study security in the smart city system. In this paper, we define the security factors for the smart city system composed of three tiers and describe the technologies for each. In addition, the design and implementation of the security layer in the Smart City middleware for the security management of the urban component in the Smart City Infrastructure and middleware, which is one of the most important issues in the Smart City system, is introduced.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.20 no.4
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• pp.25-30
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• 2010

Block Cipher SEED which was developed by KISA are not only Korea national standard algorithm of TTA but also one of standard 128-bit block ciphers of ISO/IEC. Since SEED had been developed, many analyses were tried but there was no distinguishing cryptanalysis except the 7-round differential attack in 2002. The attack used the 6-round differential characteristic with probability $2^{-124}$ and analyzed the 7-round SEED with $2^{127}$ chosen plaintexts. In this paper, we propose a new 6-round differential characteristic with probability $2^{-110}$ and analyze the 7-round SEED with $2^{113}$ chosen plaintexts.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.27 no.5
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• pp.993-1000
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• 2017

When the availability of embedded device is considered, combined countermeasure such as first-order masking and hiding countermeasures is quite attractive because the security and efficiency can be provided at the same time. Especially, combined countermeasure can be applied to the confusion and diffusion layers of the first and last rounds in order to provide the efficiency. Also, the middle rounds only employs first-order masking countermeasure or no countermeasure. In this paper, we suggest a novel side channel analysis with low complexity in the output of diffusion layer. In general, the attack target cannot be set to the output of diffusion layer owing to the high complexity. When the diffusion layer of block cipher is composed of AND operations, we show that the attack complexity can be reduced. Here, we consider that the main algorithm is SEED. Then, the attack complexity with $2^{32}$ can be reduced by $2^{16}$ according to the fact that the correlation between the combination of S-box outputs and that of the outputs of diffusion layer. Moreover, compared to the fact that the main target is the output of S-box in general, we demonstrate that the required number of traces can be reduced by 43~98% in terms of simulated traces. Additionally, we show that only 8,000 traces are enough to retrieve the correct key by suggested scheme, although it fails to reveal the correct key when performing the general approach on 100,000 traces in realistic device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.8-15
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• 2009

Side-channel attacks including the differential power analysis attack are often more powerful than classical cryptanalysis and have to be seriously considered by cryptographic algorithm's implementers. Various countermeasures have been proposed against such attacks. In this paper, we deal with the masking method, which is known to be a very effective countermeasure against the differential power analysis attack and propose new gate-level conversion methods between Boolean and arithmetic masks. The new methods require only 6n-5 XOR and 2n-2 AND gates with 3n-2 gate delay for converting n-bit masks. The basic idea of the proposed methods is that the carry and the sum bits in the ripple adder are manipulated in a way that the adversary cannot detect the relation between these bits and the original raw data. Since the proposed methods use only bitwise operations, they are especially useful for DPA-securely implementing cryptographic algorithms in hardware which use both Boolean and arithmetic operations. For example, we applied them to securely implement the block encryption algorithm SEED in hardware and present its detailed implementation result.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.2
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• pp.316-322
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• 2017

This paper suggests an efficient software implementation of lightweight encryption algorithm PRESENT which supports for secret key lengths of 80-bits. Each round of PRESENT is composed of the round key addition, substitution, and permutation and is repeated 31 times. Bo Zhu suggested combined substitution and permutation for efficient operation so that encryption throughput has been increased 2.6 times than processing substitution and permutation at separate times. The scheme that suggested in this paper improved the scheme of Bo Zhu to reduce the number of operation for the round key addition, substitution, and permutation. The scheme that suggested in this paper has increased encryption throughput up to 1.6 times than the scheme of Bo Zhu but memory usage has been increased.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4A
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• pp.291-300
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• 2002

In this paper, a way of constituting optimized S box and G function was suggested in the block cipher whose structure is similar to SEED, which is KOREA standard of 128-bit block cipher. S box can be formed with nonlinear function and an affine transform. Nonlinear function must be strong with differential attack and linear attack, and it consists of an inverse number over GF(2$\^$8/) which has neither a fixed point, whose input and output are the same except 0 and 1, nor an opposite flexed number, whose output is one's complement of the input. Affine transform can be constituted so that the input/output correlation can be the lowest and there can be no fixed point or opposite fixed point. G function undergoes diffusive linear transform with 4 S-box outputs using the matrix of 4$\times$4 over GF(2$\^$8/). G function can be constituted so that MDS(Maximum Distance Separable) code can be formed, SAC(Strict Avalanche Criterion) can be met, there can be no weak input, where a fried point, an opposite fried point, and output can be two's complement of input, and the construction of hardware can be made easy. The S box and G function suggested in this paper can be used as a constituent of the block cipher with high security, in that they are strong with differential attack and linear attack with no weak input and they are excellent at diffusion.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.207-213
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• 2019

Recently, the importance for internet of things (IoT) security has increased enormously and hardware-based compact chips are needed in IoT communication industries. In this paper, we propose low-complexity crypto-processor that unifies advanced encryption standard (AES), academy, research, institute, agency (ARIA), and CLEFIA protocols into one combined design. In the proposed crypto-processor, encryption and decryption processes are shared, and 128-bit round key generation process is combined. Moreover, the shared design has been minimized to be adapted in generic IoT devices and systems including lightweight IoT devices. The proposed crypto-processor was implemented in Verilog hardware description language (HDL) and synthesized to gate level circuit in 65nm CMOS process, which results in 11,080 gate counts. This demonstrates roughly 42% better than the aggregates of three algorithm implementations in the aspect of gate counts.