• Korean Chemical Engineering Research
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• v.46 no.2
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• pp.389-396
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• 2008

The effect of thermal cycling on bond strength and residual stress at the interface between benzocyclobutene (BCB) and plasma enhanced chemical vapor deposited (PECVD) silicon dioxide ($SiO_2$) coated silicon wafers were evaluated by four point bending and wafer curvature techniques. Wafers were bonded using a pre-established baseline process. Thermal cycling was done between room temperature and a maximum peak temperature. In thermal cycling performed with 350 and $400^{\circ}C$ peak temperature, the bond strength increased substantially during the first thermal cycle. The increase in bond strength is attributed to the relaxation in residual stress by the condensation reaction of the PECVD $SiO_2$: this relaxation leads to increases in deformation energy due to residual stress and bond strength.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.1
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• pp.7-13
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• 2013

3D stacked IC is one of the promising candidates which can keep Moore's law valid for next decades. IC can be stacked through various bonding technologies and they were reviewed in this report, for example, wafer direct bonding and atomic diffusion bonding, etc. As an effort to reduce the high temperature and pressure which were required for high bonding strength in conventional Cu-Cu thermo-compression bonding, surface activated bonding, solid liquid inter-diffusion and direct bonding interface technologies are actively being developed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.4
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• pp.175-182
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• 2017

In light emitting diode (LED) chip packaging, wire bonding is an important process that connects the LED chip on the lead frame pad with the Au wire and enables electrical operation for the next process. The wire bonding process is divided by two types: thermo compression bonding and ultrasonic bonding. Generally, the wire bonding process consists of three steps: 1st ball bonding that bonds the shape of the ball on the LED chip electrode, looping process that hangs the wire toward another connecting part with a loop shape, and 2nd stitch bonding that forms and bonds to another electrode. This study analyzed the factors affecting the LED die bonding processes to optimize the process capability that bonds a small Zener diode chip on the PLCC (plastic-leaded chip-carrier) LED package frame, and then applied response surface analysis. The design of experiment (DOE) was established considering the five factors, three levels, and four responses by analyzing the factors. As a result, the optimal conditions that meet all the response targets can be derived.

• Korean Chemical Engineering Research
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• v.46 no.3
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• pp.619-625
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• 2008

The effects of thermal cycling on residual stresses in both inorganic passivation/insulating layer that is deposited by plasma enhanced chemical vapor deposition (PECVD) and organic thin film that is used as a bonding adhesive are evaluated by 4 point bending method and wafer curvature method. $SiO_2/SiN_x$ and BCB (Benzocyclobutene) are used as inorganic and organic layers, respectively. A model about the effect of thermal cycling on residual stress and bond strength (Strain energy release rate), $G_c$, at the interface between inorganic thin film and organic adhesive is developed. In thermal cycling experiments conducted between $25^{\circ}C$ and either $350^{\circ}C$ or $400^{\circ}C$, $G_c$ at the interface between BCB and PECVD $ SiN_x $ decreases after the first cycle. This trend in $G_c$ agreed well with the prediction based on our model that the increase in residual tensile stress within the $SiN_x$ layer after thermal cycling leads to the decrease in $G_c$. This result is compared with that obtained for the interface between BCB and PECVD $SiO_2$, where the relaxation in residual compressive stress within the $SiO_2$ induces an increase in $G_c$. These opposite trends in $G_cs$ of the structures including either PECVD $ SiN_x $ or PECVD $SiO_2$ are caused by reactions in the hydrogen-bonded chemical structure of the PECVD layers, followed by desorption of water.

• 전기의세계
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• v.39 no.6
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• pp.42-49
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• 1990

반도체 조립과 관련하여 다이본딩 시스템, 와이어본딩 시스템 및 인라인 시스템의 구성 및 기능을 살펴보고, 자동화를 위해 필요한 관리제어, 시각처리 및 통신에 대하여 간략하게 알아보고자 한다.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.41 no.6
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• pp.443-453
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• 2017

In flip chip technology, the conventional solder bump has been replaced with a copper (Cu) pillar bump owing to its higher input/output (I/O) density, finer pitch, and higher reliability. However, Cu pillar bump technology faces several issues, such as interconnect shorting and higher low-k stress due to stiffer Cu pillar structure when the conventional reflow process is used. Therefore, the thermal compression bonding (TCB) process has been adopted in the flip chip attachment process in order to reduce the package warpage and stress. In this study, we investigated the package warpage induced during the TCB process using a numerical analysis. The warpage of the TCB process was compared with that of the reflow process.

• Korean Chemical Engineering Research
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• v.45 no.5
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• pp.466-472
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• 2007

A technology platform for wafer-level three-dimensional integration circuits (3D-ICs) is presented, and that uses wafer bonding with low-k polymeric adhesives and Cu damascene inter-wafer interconnects. In this work, one of such technical platforms is explained and characterized using a test vehicle of inter-wafer 3D via-chain structures. Electrical and mechanical characterizations of the structure are performed using continuously connected 3D via-chains. Evaluation results of the wafer bonding, which is a necessary process for stacking the wafers and uses low-k dielectrics as polymeric adhesive, are also presented through the wafer bonding between a glass wafer and a silicon wafer. After wafer bonding, three evaluations are conducted; (1) the fraction of bonded area is measured through the optical inspection, (2) the qualitative bond strength test to inspect the separation of the bonded wafers is taken by a razor blade, and (3) the quantitative bond strength is measured by a four point bending. To date, benzocyclobutene (BCB), $Flare^{TM}$, methylsilsesquioxane (MSSQ) and parylene-N were considered as bonding adhesives. Of the candidates, BCB and $Flare^{TM}$ were determined as adhesives after screening tests. By comparing BCB and $Flare^{TM}$, it was deduced that BCB is better as a baseline adhesive. It was because although wafer pairs bonded using $Flare^{TM}$ has a higher bond strength than those using BCB, wafer pairs bonded using BCB is still higher than that at the interface between Cu and porous low-k interlevel dielectrics (ILD), indicating almost 100% of bonded area routinely.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.05a
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• pp.202-202
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• 2004

화합물 반도체는 초고속, 초고주파 디바이스에 적합한 재료인 갈큠비소(GaAs), 인듐-인산듐(InP) 등 2 개 이상의 원소로 구성되어 있고, 실리콘에 비해 결정내의 빠른 전자이동속도와 발광성, 고속동작, 고주파특성, 내열특성을 지니고 있어 발광 소자 (LED)와 이동통신(RE)소자의 개발 등에 다양하게 이용되고 있다. 이와 같이 화합물 반도체는 고부가가치의 첨단산업 부품들로 적용되는 만큼 생산제조 공정에 해당하는 연마, 본딩, 디본딩에 관한 방법과 기술에 대한 연구가 꾸준히 진행되고 있다.(중략)

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.37-41
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• 2012

The wafer level stacking with Cu-to-Cu bonding becomes an important technology for high density DRAM stacking, high performance logic stacking, or heterogeneous chip stacking. Cu CMP becomes one of key processes to be developed for optimized Cu bonding process. For the ultra low-k dielectrics used in the advanced logic applications, Ti barrier has been preferred due to its good compatibility with porous ultra low-K dielectrics. But since Ti is electrochemically reactive to Cu CMP slurries, it leads to a new challenge to Cu CMP. In this study Ti barrier/Cu interconnection structure has been investigated for the wafer level 3D integration. Cu CMP wafers have been fabricated by a damascene process and two types of slurry were compared. The slurry selectivity to $SiO_2$ and Ti and removal rate were measured. The effect of metal line width and metal density were evaluated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.340-341
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• 2008

본 논문에서는 미세 패턴을 구현하기 위해 폴리머 소재의 조성에 따른 공정의 영향에 대해서 연구를 하였다. 제작된 본딩 필름은 난연계 에폭시수지와 고내열 특성을 위해서 경화제 조화 성분 폴리머를 이용하였다. 또한, CTE 값을 향상하기 위해서 필러로서 SiO2 분말을 이용하였다. 조성물은 혼합하여 슬러리를 만들고, 테입 캐스터를 이용하여 필름을 제작하였다. 제작된 필름은 150 및 160도의 온도에서 가열 가압하여 경화하였다. 제작된 수지는 유전율 3.2의 유전율과 loss tan 6값이 0.015값을 나타내었다. 또한 제작된 본딩 필름의 조화특성 연구를 위해서 경화조건, 스웰링 조건, 디스미어 시간에 따른공정 변화의 영향에 대해 고찰하였으며 제작된 시편의 조도는 SEM으로 관찰하여 조화성분 함량에 따른 최적 조건을 선정하였다.