• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.2
• /
• pp.363-371
• /
• 2013

This paper describes a multi-standard LDPC decoder which supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A DFU(decoding function unit) based on sign-magnitude arithmetic is used for hardware reduction. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.13-${\mu}m$ CMOS cell library. It has 312,000 gates and 70,000 bits RAM. The estimated throughput is about 79~210 Mbps at 100 MHz@1.8v.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.4
• /
• pp.786-792
• /
• 2016

Camellia was jointly developed by Nippon Telegraph and Telephone Corporation and Mitsubishi Electric Corporation in 2000. Camellia specifies the 128-bit message block size and 128-, 192-, and 256-bit key sizes. In this paper, a modified round operation block which unifies a register setting for key schedule and a conventional round operation block is proposed. 16 ROMs needed for key generation and round operation are implemented using only 4 dual-port ROMs. Due to the use of a message buffer, encryption/decryption can be executed without a waiting time immediately after KA and KB are calculated. The suggested block cipher Camellia algorithm is designed using Verilog-HDL, implemented on Virtex4 device and operates at 184.898MHz. The designed cryptographic core has a maximum throughput of 1.183Gbps in 128-bit key mode and that of 876.5Mbps in 192 and 256-bit key modes. The cryptographic core of this paper is applicable to security module of the areas such as smart card, internet banking, e-commerce and satellite broadcasting.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.11
• /
• pp.2517-2524
• /
• 2012

This paper describes an efficient implementation of KS(Korea Standards) block cipher algorithm ARIA. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit and four modes of operation including ECB, CBC, OFB and CTR. A hardware sharing technique, which shares round function in encryption/decryption with key initialization, is employed to reduce hardware complexity. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a $0.13-{\mu}m$ CMOS cell library. It has 46,100 gates on an area of $684-{\mu}m{\times}684-{\mu}m$ and the estimated throughput is about 1.28 Gbps at 200 MHz@1.2V.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.8
• /
• pp.67-74
• /
• 2008

A compact and high-performance AES(Advanced Encryption Standard) encryption/decryption processor is designed by applying various hardware sharing and optimization techniques. In order to achieve minimized hardware complexity, sharing the S-Boxes for round transformation with the key scheduler, as well as merging and reusing datapaths for encryption and decryption are utilized, thus the area of S-Boxes is reduced by 25%. Also, the S-Boxes which require the largest hardware in AES processor is designed by applying composite field arithmetic on $GF(((2^2)^2)^2)$, thus it further reduces the area of S-Boxes when compared to the design based on $GF(2^8)$ or $GF((2^4)^2)$. By optimizing the operation of the 64-bit round transformation and round key scheduling, the round transformation is processed in 3 clock cycles and an encryption of 128-bit data block is performed in 31 clock cycles. The designed AES processor has about 15,870 gates, and the estimated throughput is 412.9 Mbps at 100 MHz clock frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.05a
• /
• pp.132-135
• /
• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2013.10a
• /
• pp.409-411
• /
• 2013

In this paper, we used FTN(Faster than Nyquist) method that is transmission method faster than Nyquist theory. FTN signaling introduces intersymbol interference(ISI), but increases the bit rate while preserving the signaling bandwidth. Therefore, we need compensating ISI caused by FTN. In this paper, we propose decoding method for FTN signal that using BCJR Equalizer and Turbo Equalization. first ISI of inputted signal is restored by BCJR Equalizer, and then restored signal inputted in LDPC decoder, and repeat the process using the Turbo Equalization improves performance. finally, we shows performance comparison according to reduce percentage of FTN signal.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.11C
• /
• pp.889-895
• /
• 2010

MIMO system generally requires more than one antenna at the communication device. However, many wireless devices are limited by size, cost or hardware complexity to one antenna. To overcome such restrictions, we used a new technique, called cooperative communication. We propose a new cooperative transmission strategy system using cross-layer coding method base on H-ARQ for optimal communication. Proposed cooperative H-ARQ system that can improve the above problems and can get the better performance. In proposed cooperative system with H-ARQ method, if the received signal from source node is satisfied by the destination preferentially, the destination transmit ACK message to both relay node and source node, and then recovers the received signal. In addition, if ARQ message indicates NACK message, relay node operates selective retransmission. Based on the simulation results in aspect to BER performance and throughput, the proposed method which combined cooperative system with H-ARQ based on cross-layer coding can improve spectral efficiency reliability of system compared with that of general one by one system.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.7
• /
• pp.1332-1340
• /
• 2007

This paper describes an efficient hardware design of key wrap/unwrap algorithm for security layer of WiBro system. The key wrap/unwrap core (WB_KeyWuW) is based on AES (Advanced Encryption Standard) algorithm, and performs encryption/decryption of 128bit TEK (Traffic Encryption Key) with 128bit KEK (Key Encryption Key). In order to achieve m area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented by using field transformation technique. As a result, the gate count of the WB_KeyWuW core is reduced by about 25% compared with conventional LUT (Lookup Table)-based design. The WB_KeyWuW con designed in Verilog-HDL has about 14,300 gates, and the estimated throughput is about $16{\sim}22-Mbps$ at 100-MHz@3.3V, thus the designed core can be used as an IP for the hardware design of WiBro security system.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.5
• /
• pp.1256-1265
• /
• 1996

Soft-decision detectors are used in many FEC and ARQ schemes to enhance the bit-error-probability and system throughput. Also, the hybrid-ARQ protocol is a very efficient schemeto achieve overall performance improvement. In this paper, we propose a new hybrid-ARQ protocol based on the first-order Reed-Muller codes employing soft-decision detectors. The Reed-Muller codes have the virtue of being able to use the fast Green machine decoder that is simple to implement. As the performance measures, the bit-error-probability and system throughput are evaluted for the proposed hybrid-ARQ procol, and compared with those of other hybrid-ARQ schemes. It is shown that the use of the proposed hybrid-ARQ protocol results in significant performance improvement without causing much loss in view of system complexity.

• Journal of Internet Computing and Services
• /
• v.8 no.4
• /
• pp.61-70
• /
• 2007

In this paper, we propose and observe the Adaptive Modulation system with optimal Turbo Coded V-BLAST(Vertical-Bell-lab Layered Space-Time) technique that is applied the extrinsic information from MAP Decoder in decoding Algorithm of V-BLAST: ordering and slicing. And comparing the proposed system with the Adaptive Modulation system using conventional Turbo Coded V-BLAST technique that is simply combined V-BLAST with Turbo Coding scheme, we observe how much throughput performance and SNR has been improved. In addition, we show that the proposed system using STD(Selection Transmit Diversity) scheme results in on improved result, By using simulation and comparing to conventional Turbo Coded V-BLAST technique with the Adaptive Modulation systems, the optimal Turbo Coded V-BLAST technique with the Adaptive Modulation systems has SNR gain over all SNR range and better throughput gain that is about 350Kbps in 11dB SNR range. Also, comparing with the conventional Turbo Coded V-BLAST technique using 2 transmit and 2 receive antennas, the proposed system with STD scheme show that the improvement of maximum throughput is about 1.77Mbps in the same SNR range and the SNR gain is about 5.88dB to satisfy 4Mbps throughput performance.