• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.6
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• pp.1323-1329
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• 2014

In this paper, we analyzed efficient decoding scheme with FTN (Faster than Nyquist) method that is transmission method faster than Nyquist theory and increase the throughput. we proposed viterbi equalizer model to minimize ISI (Inter-Symbol Interference) when FTN signal is transmitted. the proposed model utilized interference as branch information. In this paper, to decode FTN singal, we used turbo equalization algorithms that iteratively exchange probabilistic information between soft Viterbi equalizer (BCJR method) and LDPC decoder. By changing the trellis diagram in order to maximize Euclidean distance, we confirmed that performance was improved compared to conventional methods as increasing throughput of FTN signal.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.39-49
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• 2011

Turbo code needs long decoding time because of iterative decoding. To communicate with high speed, we have to shorten decoding time and it is possible with parallel process. But memory contention can cause from parallel process, and it reduces performance of decoder. To avoid memory contention, QPP interleaver is proposed in 2006. In this paper, we propose MDF method which is fit to QPP interleaver, and has relatively short decoding time and reduced logic. And introduce the design of MAP decode module using MDF method. Designed decoder is targetted to FPGA of Xilinx, and its throughput is 80Mbps maximum.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12C
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• pp.1222-1230
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• 2005

We aim at increasing the throughput of the hybrid automatic retransmission request (HARQ) protocol in Space-Time (ST) coded multi-antenna transmission systems. By utilizing reliability information at the decoder, we obtain an improved probability of successful decoding, which enhances the overall system throughput at low-complexity. Simulations and analytical results demonstrate the performance of our scheme in impulse noise environment as well as AWGN and fading multi-input multi-ouput (MIMO) channels.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8C
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• pp.763-770
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• 2006

In this paper, a variable Reed-Solomon(RS) decoder with erasure decoding functionality is designed based on the modified Euclid's algorithm(MEA). The variability of the decoder is implemented through shortening and puncturing based on the RS(124, 108, 8) code, other than the primitive RS(255, 239, 8) code. This leads to shortening the decoding latency. The decoder performs 4-step pipelined operation, where each step is designed to be clocked by an independent clock. Thus by using a faster clock for the MEA block, the complexity and the decoding latency can be reduced. It can support both continuous- and burst-mode decoding. It has been designed in VHDL and synthesized in an FPGA chip, consuming 3,717 logic cells and 2,048-bit memories. The maximum decoding throughput is 33 MByte/sec.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.27-36
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• 2005

This paper presents an area-efficient architecture to implement the high-speed Reed-Solomon(RS) decoder, which is used in a variety of communication systems such as wireless and very high-speed optical communications. We present the new pipelined-recursive Modified Euclidean(PrME) architecture to achieve high-throughput rate and reducing hardware-complexity using folding technique. The proposed pipelined recursive architecture can reduce the hardware complexity about 80$\%$ compared to the conventional systolic-array and fully-parallel architecture. The proposed RS decoder has been designed and implemented with the 0.13um CMOS technology in a supply voltage of 1.2 V. The result show that total number of gate is 393 K and it has a data processing rate of S Gbits/s at clock frequency of 625 MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.72-79
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• 2014

This paper presents a method for constructing a pipeline-aware quasi-cyclic irregular repeat accumulate low-density parity-check (PA-QC-IRA-LDPC) codes and efficient rate-1/2 (2016, 1008) PA-QC-IRA-LDPC decoder architecture. A novel pipeline scheduling method is proposed. The proposed methods efficiently reduce the critical path using pipeline without any bit error rate (BER) degradation. The proposed pipeline-aware LDPC decoder provides a significant improvement in terms of throughput, hardware efficiency, and energy efficiency. Synthesis and layout of the proposed architecture is performed using 90-nm CMOS standard cell technology. The proposed architecture shows more than 53% improvement of area efficiency and much better energy efficiency compared to the previously reported architectures.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.2
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• pp.849-855
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• 2012

In this paper, a proposed system can be ensured safety using scrambling technique in order to protect personal information which identifies visually from the existing e-passport. This system inserts ID card number and photograph into e-passport using scrambling technique. In this system, we need user private key and CA private key to encrypt and decrypt which make it secure. And It show better performance in throughput by not encrypting or decrypting the whole e-passport.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.385-390
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• 2013

This paper proposes an efficient hardware architecture of CABAC for HEVC decoder. The proposed method is structured to handle two bins in one cycle, while preserving data dependencies of the CABAC. In addition, the processing time of the proposed architecture is reduced because the operation using Offset and Range is processed while the architecture reads rLPS from rLPSROM. As a result of analyzing operating frequency of the proposed CABAC architecture, the proposed architecture has improved by 40% than the previous one.

• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.275-280
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• 2010

In this paper, we discuss and propose an efficiently parallelized block cipher algorithm on the CELL BE processor. With considering the heterogeneous feature of the CELL BE architecture, we apply different encoding/decoding methods to PPE and SPE and improve the throughput. Our implementation was fully tested, with execution results showing achievement of high throughput, capable of supporting as high network speed as 2.59 Gbps. Compared to various parallel implementations on multi-core systems, our approach provides speedup of 1.34 in terms of encoding/decoding speed.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.51-62
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• 2003

This paper presents a novel survivor memeory management and decoding techniques with sequential backward state transition control in the trace back Viterbi decoder. The Viterbi algorithm is an maximum likelihood decoding scheme to estimate the likelihood of encoder state for channel error detection and correction. This scheme is applied to a broad range of digital communication such as intersymbol interference removing and channel equalization. In order to achieve the area-efficiency VLSI chip design with high throughput in the Viterbi decoder in which recursive operation is implied, more research is required to obtain a simple systematic parallel ACS architecture and surviver memory management. As a method of solution to the problem, this paper addresses a progressive decoding algorithm with sequential backward state transition control in the trace back Viterbi decoder. Compared to the conventional trace back decoding techniques, the required total memory can be greatly reduced in the proposed method. Furthermore, the proposed method can be implemented with a simple pipelined structure with systolic array type architecture. The implementation of the peripheral logic circuit for the control of memory access is not required, and memory access bandwidth can be reduced Therefore, the proposed method has characteristics of high area-efficiency and low power consumption with high throughput. Finally, the examples of decoding results for the received data with channel noise and application result are provided to evaluate the efficiency of the proposed method.