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Design of an Area-Efficient Reed-Solomon Decoder using Pipelined Recursive Technique  

Lee, Han-Ho (School of Information ' Communication)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.7, 2005 , pp. 27-36 More about this Journal
Abstract
This paper presents an area-efficient architecture to implement the high-speed Reed-Solomon(RS) decoder, which is used in a variety of communication systems such as wireless and very high-speed optical communications. We present the new pipelined-recursive Modified Euclidean(PrME) architecture to achieve high-throughput rate and reducing hardware-complexity using folding technique. The proposed pipelined recursive architecture can reduce the hardware complexity about 80$\%$ compared to the conventional systolic-array and fully-parallel architecture. The proposed RS decoder has been designed and implemented with the 0.13um CMOS technology in a supply voltage of 1.2 V. The result show that total number of gate is 393 K and it has a data processing rate of S Gbits/s at clock frequency of 625 MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.
Keywords
error correction; area-efficient; Reed-Solomon coding; pipelined, recursive.;
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