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Design of a Variable Shortened and Punctured RS Decoder  

Song Moon-Kyou (원광대학교 전기전자 및 정보공학부 무선통신연구실)
Kong Min-Han (원광대학교 전기전자 및 정보공학부 무선통신연구실)
Lim Myoung-Seob (전북대학교 전자정보공학부 초고속데이터이동통신연구실)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.31, no.8C, 2006 , pp. 763-770 More about this Journal
Abstract
In this paper, a variable Reed-Solomon(RS) decoder with erasure decoding functionality is designed based on the modified Euclid's algorithm(MEA). The variability of the decoder is implemented through shortening and puncturing based on the RS(124, 108, 8) code, other than the primitive RS(255, 239, 8) code. This leads to shortening the decoding latency. The decoder performs 4-step pipelined operation, where each step is designed to be clocked by an independent clock. Thus by using a faster clock for the MEA block, the complexity and the decoding latency can be reduced. It can support both continuous- and burst-mode decoding. It has been designed in VHDL and synthesized in an FPGA chip, consuming 3,717 logic cells and 2,048-bit memories. The maximum decoding throughput is 33 MByte/sec.
Keywords
block code; error correcting code; modified Euclid's algorithm; variable RS code;
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