• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.7A
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• pp.1227-1233
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• 2001

본 논문에서는 유전자 알고리즘을 기반으로 한 새로운 다중사용자 복조기를 제안하고, 최적(optimum) 다중사용자 복조기의 Hopfield 신경망 다중사용자 복조기를 비교 대상으로 하여 원근문제가 존재하는 환경에서 컴퓨터 시뮬레이션을 통해서 비트오율 성능을 비교하였다. 시뮬레이션 결과, 원근문제에 존재하는 채널환경에서는 본 논문에서 제안한 구조는 상당히 적은 계산량으로 최적의 다중사용자 복조기와 Hopfield 다중사용자 복조기와 근접한 성능을 기대할 수 있었고, 원근문제가 존재하지 않는 경우에서는 Hopfield 신경망구조보다 우월한 성능향상을 얻을 수 있었다.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1568_1569
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• 2009

RFID 수동 태그의 동작 원리를 이용하여 USN/WBAN 센서 노드 시스템에 적용 가능한 웨이크 업 회로를 설계하였다. 웨이크 업회로 구성은 크게 전압 체배기, 복조기, 상태기계로 구성되었다. 상태 기계에 동작 가능한 전압을 공급하기 위해 전압 체배기는 문턱 전압 제거 방식을 적용한 구조를 사용하였고, 복조기 회로로는 AM 복조기로 구조가 간단한 포락선 검파기 방식을 사용하였다. 전압 체배기에 높은 전압이 인가될 경우 회로가 파괴되는 것을 막기 위해 제한 회로를 구성하여 최대 전압을 2.1V로 제한하였다. 또한 복조기에서는 안정적인 데이터 복조를 위해 비교기의 기준전압을 입력신호의 평균값을 사용한 슈미트 트리거 비교기를 사용하여 안정적으로 데이터를 추출하였다. 삼성 0.18um CMOS 공정을 이용하여 설계하였고, 측정 결과 전압 체배기의 체배 전압은 2.07~1.76V까지 체배 되는 것을 확인하였고, 복조기의 데이터 복조 역시 약 4M의 거리까지 데이터를 복조함을 확인하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2A
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• pp.147-156
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• 2004

This paper presents an implementation and performance analysis of an access channel decoder which exploits a diversity gain due to the independent magnitude of received signals energy at each of antenna elements of a smart antenna BTS (Base-station Transceiver Subsystem) operating in CDMA2000 1X signal environment. Proposed access channel decoder consists of a searcher supporting 4 fingers, Walsh demodulator, and demodulator controller. They have been implemented with 5 of 1 million-gate FPGA's (Field Programmable Gate Array) Altera's APEX EP20K1000EBC652 and TMS320C6203 DSP (digital signal processing). The objective of the proposed access channel decoders is to enhance the data retrieval at co]1-site during the access period, for which the optimal weight vector of the smart antenna BTS is not available. Through experimental tests, we confirmed that the proposed access channel decoder exploitng the diversity technique outperforms the conventional one, which is based on a single antenna channel, in terms of detection probability of access probe, access channel failure probability, and $E_{b/}$ $N_{o}$ in Walsh demodulator.r.r.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.5
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• pp.877-883
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• 2001

In this paper, we propose a new Genetic Algorithm(GA)-based Multiuser Detector(MUD), and its performance is evaluated by computer simulation compared to both the optimum MUD and the Hopfield neural network(NN) -based MUD when the near-far problem exists. From the results of comprehensive simulation, it is shown that the proposed MUD in this paper can guarantee a close BER performance compared to both the optimum MUD and the Hopfield NN MUD with a considerable reduced complexity under the near-far condition. Furthermore, a more performance improvement than the Hopfield W MUD can be expected when the near-far problem does not exist.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.4
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• pp.591-601
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• 1993

In this paper, the relationship between k consecutive outputs of the conventional differential detector and output of differential detector with k-bit delayer MSK and GMSK signal, using a k-bit delay circuit, is the product of k successive output of the conventional differential detector. This relationships are used to generalize the structure of receiver which was proposed by Makrakis using 2-bit delay line. The error rate performance of the proposed method is carried out by computer simulation and significant performance improvement is achieved for differential MSK and GMSK system.

• Journal of Korea Society of Industrial Information Systems
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• v.8 no.1
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• pp.83-91
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• 2003

High-speed QPSK demodulator has been in important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes all-digital QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. All-digital QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tacking to fabricate FPGA chip. The testing results of the implemented onto CPLD-EPF10K100GC 503-4 chip show demodulation speed is reached up to 2.6[Mbps]. If it is implemented a CPLD chip with speed grade 1, the demodulation speed can be faster by about 5 times. Actually in case of designing by ASIC, its speed my be faster than CPLD by 5 times. Therefore, it is possible to fabricate the all-digital QPSK demodulator chipset with speed of 50[Mbps].

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.10C
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• pp.995-1006
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• 2003

It is well know that in the wireless communication systems the transmitted signals can suffer from multipath fading due to the wave propagation characteristics and the obstacles over the paths, resulting in serious reduction in the power of the received signals. However, it is possible to take advantage of the inherent diversity imposed in the multipath reception if the underlying channel can be properly estimated. One of the diversity reception methods in this case is Rake processing. In this paper we study the Rake receivers for the direct-sequence spread-spectrum communication systems utilizing PN (pseudo noise) sequences to achieve spread spectrum. A conventional Rake receiver can use the finite-duration impulse (FIR) filter followed by the PN sequence demodulator, where the FIR filter coefficients are the reverse-ordered complex conjugate values of the fading channel impulse response estimates. Here, we propose a new Rake processing method by replacing the aforementioned PN code sequence with a new set of optimum demodulator coefficients. More specifically, the concept of the new optimum Rake processing is first introduced and then the optimum demodulator coefficients are theoretically derived. The performance obtained using the new optimum Rake processing is also calculated. The analytical results are verified by computer simulation. As a result, it is shown that the new optimum Rake processing method improves the MSE performance more than 10 dB over the conventional one using the fixed PN sequence demodulator. It is also shown that the new optimum Rake processing method improves the MSE performance about 10 dB over the Adaptive Correlator that performs the combining of the multipath components and PN demodulation concurrently. And finally, the MSE performance of the optimum Rake demodulator is very close to the MSE performance of OPSK demodulator under the AWGN channel.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.226-230
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• 2000

In this paper, we implemented the QPSK demodulator with a CPLD chip, and examined the results. DD(Decision Directed)-Gardner algorithm is used for STR loop and Decision-Directed algorithm is used for CPR loop. The speed of the QPSK demodulator implemented in FLEX10K chip can be guaranteed approximately 2[Mbpsl] transmission speed. In practical designed by ASIC, the speed is faster than that of CPLD by 5-6 times.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.7-13
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• 2011

A mixed-mode QPSK demodulator for 60-GHz wireless personal area network application is demonstrated. In this work, mixed-mode QPKS demodulation scheme achieving low power consumption and small area is employed. The prototype chip realized by 60-nm CMOS Logic process can demodulate up to 4.8-Gb/s QPSK signals at 4.8-GHz carrier frequency. At this carrier frequency, the demodulator core consumes 54 mW from 1.2-V power supply while the chip area is $150{\times}150{\mu}m^2$. Using the fabricated chip, transmission and demodulation of 1.7-GSymbol/s QPSK signal in 60-GHz link is demonstrated.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.287-292
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• 2012

In this paper, design of a conductivity detector using a synchronous demodulation is presented to detect the electric conductivity of liquids with low noise. For the purpose, the detector is constructed by the combination of a carrier generator, conductivity detecting cell, and synchronous demodulator. The signal-to-noise ratio(SNR) of the detector is improved by adjusting the frequency bandwidth of the demodulator, whereby infinitesimal conductivity signals can easily be measured under various noise environments. As an application example, a conductivity detector, which is applied to the air monitoring in a fabrication process of semiconductor chips, is designed using the synchronous demodulation. The validity of the design technique is verified by experiments. Since experimental results are shown to approach the design performance of the detector, the synchronous demodulation proves to be useful to the design of a conductivity detector for measuring the infinitesimal electric conductivity of liquids.