• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.65-72
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• 2008

This paper proposes a new dual-loop digital PLL(DPLL) using seamless frequency tracking methods. The dual-loop construction, which is composed of the coarse and fine loop for fast locking time and a switching noise suppression, is used successive approximation register technique and TDC. The proposed DPLL in order to compensate the quality of jitter which follows long-term of input frequency is newly added cord conversion frequency tracking method. Also, this DPLL has VCO circuitry consisting of digitally controlled V-I converter and current-control oscillator (CCO) for robust jitter characteristics and wide lock range. The chip is fabricated with Dongbu HiTek $0.18-{\mu}m$ CMOS technology. Its operation range has the wide operation range of 0.4-2GHz and the area of $0.18mm^2$. It shows the peak-to-peak period jitter of 2 psec under no power noise and the power dissipation of 18mW at 2GHz through HSPICE simulation.

• Journal of the Korean Magnetics Society
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• v.24 no.4
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• pp.123-127
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• 2014

We developed a digital 3-axis flux-gate magnetometer for magnetic field signal measurement from warship during demagnetizing and degaussing processes. For the magnetometer design, we considered following points; the distance between magnetic field measurement station and magnetometer located under sea is about several 100 m, the magnetometer is exposed to magnetic field of ${\pm}1mT$ during demagnetizing process, and magnetometer is located under the sea about 30 m depth. To overcome long distance problem, magnetometer could be operated on wide input supply voltage range of 16~36 V using DC/DC converter, and for the data communication between the magnetometer and measurement station a RS422 serial interface was employed. To improve perming effect due to the ${\pm}1mT$ during demagnetizing process, magnetometer could be compensated external magnetic field up to ${\pm}1mT$ but magnetic field measuring rang is only ${\pm}100{\mu}T$. The perming effect was about ${\pm}2nT$ under ${\pm}1mT$ external magnetic field. The magnetometer was tested water vessel with air pressure up to 6 bar for the sea water pressure problems. Linearity of the magnetometer was better than 0.01 % in the measuring range of ${\pm}0.1mT$ and noise level was $30pT/\sqrt{Hz}$ at 1 Hz.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.70-77
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• 2013

We suggest a low area and high efficiency switched-mode power supply (SMPS) with a pulse width modulation (PWM) generator based on a pseudo relaxation-oscillating technique. In the proposed circuit, the PWM duty ratio is determined by the voltage slope control of an internal capacitor according to amount of charging current in a PWM generator. Compared to conventional SMPSs, the proposed control method consists of a simple structure without the filter circuits needed for an analog-controlled SMPS or the digital compensator used by a digitally-controlled SMPS. The proposed circuit is able to operate at switching frequency of 1MHz~10MHz, as this frequency can be controlled from the selection of one of the internal capacitors in a PWM generator. The maximum current of the core circuit is 2.7 mA, and the total current of the entire circuit including output buffer driver is 15 mA at 10 MHz switching frequency. The proposed SMPS has a simulated maximum ripple voltage of 7mV. In this paper, to verify the operation of the proposed circuit, we performed simulation using Dongbu Hitek BCD $0.35{\mu}m$ technology and measured the proposed circuit.

• Proceedings of the Korean Society for Bio-Environment Control Conference
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• 2001.04b
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• pp.100-102
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• 2001

본 연구에서는 온실의 난방에 사용되는 열풍식 난방기 등의 배기 연통에 부착하여 배출되는 가스로부터 열을 회수할 수 있는 장치를 개발함에 있어서 연통과 열회수 장치간의 열 교환 성능을 3가지 상이하게 설계된 열 교환 장치(Fig. 1 참조)에 대하여 실험적으로 비교 분석하였다. Fig. 1-(a)는 열 교회수기 개발을 위해 기존에 사용한 장치로서 회수용 공기의 흐름방향이 배기 연통과 직각을 이룬 형식이며, Fig. 1-(b) 및 (c)는 열 회수 성능 개선을 위해 새로 설계된 형식으로서 각각 열 교환 파이프의 배치형식이 상이하나 회수용 공기의 흐름방향이 180도로 굴곡되는 U-자형 흐름이 이루어지도록 하였다. 실험에 사용된 공기 순환 펜의 용량은 AB-형의 경우에는 최대 25㎥/min이고, C-형 및 D-형의 경우는 공히 최대 42㎥/min으로서 송풍전압 조절장치를 이용하여 풍량을 연속적으로 조절할 수 있도록 하였다. U-자형 흐름형식인 C-형 및 D-형의 경우 흐름 방향의 굴곡으로 인한 마찰저항이 있을 것으로 예상은 했으나 당초 예상했던 것에 비해 마찰 저항이 지나치게 큰 것으로 밝혀졌다. 비록 설계된 열교환 튜브의 배열형식별 열 교환기의 외부 모양이 달라 회수기의 표면을 통한 대류 열 교환이 다소 차이를 보일 것으로 예상되지만 본 연구에서는 열 회수장치에 내장된 열 교환 튜브부분만을 통한 열 회수율을 중심으로 형식간의 성능을 비교하였다. 실험을 통하여 측정된 자료중 대표적인 예는 Fig-2와 같으며, 측정자료를 기준으로 분석된 열회수 성능에 대한 설계형식별 비교 결과는 Table-1과 같으며, 분석된 결과를 요약하면 다음과 같다: 1. AB-형 열회수시스템의 경우, 초기 투자비용과 현재의 농용 전력요금 하에서 에너지 절감규모를 비교하면, 대체로 1년을 전후하여 투자에 대한 보상이 충분히 가능할 것으로 판단된다. 2. C-형 및 D-형 열회수시스템의 경우, 열 회수용 공기의 흐름방향이 동일 공간내에서 180도 굴절됨으로서 저항이 크게 발생되어 송풍 펜의 전압 증가에 따른 유속증가가 미미하였으며, 굴절형의 열교환장치는 비록 열교환면적은 직선형과 유사하더라도 송풍 펜의 공기저항이 커져서 결국 열 회수성능이 기대했던 것만큼 크게 개선되지는 못했다. 3. 송풍펜의 용량은 AB-형에 사용된 용량인 25㎥/min 전후가 적절할 것으로 판단되며, 적정 송풍 펜용량 하에서 열 회수성능은 굴절형이 직선형보다 효과적인 것으로 나타났다. 다만, 곡선형은 물론 직선형에서도 열교환 튜브의 배치밀도, 튜브 길이 및 두께 등의 변화에 따른 최적화 연구가 수반되어야 할 것으로 판단된다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.2
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• pp.139-145
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• 2024

This paper presents the design of a voltage controlled oscillator (VCO) which is one of the key building blocks in modern wireless communication systems with small VCO gain (K_vco) variation. To compensate conventional large K_vco variation, a series varactor bank has been added to the conventional LC-tank with parallel capacitor bank array. And also, in order to achieve excellent phase noise performance while maintaining wide tuning range, a mixed coarse/fine tuning scheme(series varactor array and parallel capacitor array) is chosen. The switched varactor array bank is controlled by the same digital code for switched capacitor array without additional digital circuits. For use at a low voltage of 1.2V, the proposed current reference circuit in this paper used a current reference circuit for safety with the common gate removed more safely. Implemented in a TSMC 0.13㎛ CMOS RF technology, the proposed VCO can be tuned from 4.4GH to 5.3GHz with the K_vco (VCO gain ) variation of less than 9.6%. While consuming 3.1mA from a 1.2V supply, the VCO has -120dBc/Hz phase noise at 1MHz offset from the carrier of the 5.3 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.902-911
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• 2003

Using InGaP/GaAs HBT power cells with a 2.0${\times}$20$\mu\textrm{m}$$^2$ emitter area of a unit HBT, a two stage MMIC power amplifier has been developed for IMT-2000 handsets. An active-bias circuit has been used for temperature compensation and reduction in the idling current. Fitting on measured S-parameters of the HBT cells, circuit elements of HBT's nonlinear equivalent model have been extracted. The matching circuits have been designed basically with the extracted model. A two stage HBT MMIC power amplifier fabricated using ETRI's HBT process. The power amplifier produces an 1-㏈ compressed output power(P$\_$l-㏈/) of 28.4 ㏈m with 31% power added efficiency(PAE) and 23-㏈ power gain at 1.95 GHz in on-wafer measurement. Also, the power amplifier produces a 26 ㏈m output power, 28% PAE and a 22.3-㏈ power gain with a -40 ㏈c ACPR at a 3.84 ㎒ off-center frequency in COB measurement.quency in COB measurement.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.2
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• pp.199-208
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• 2012

This paper proposes a quasi Z-source DVR(Dynamic Voltage Restorer) system with a series connection of the output terminals, to compensate the voltage variations in the 6.6[kV]/60[Hz] power distribution system. The conventional DVR using one quasi Z-source AC-AC converter has the advantage which it can compensate the voltage variations without the need for the additional energy storage device such as a battery, but it is impossible to compensate for the 50[%] under voltage sags. To solve this problem, a DVR system using two quasi Z-source AC-AC converters with the series connection of the output terminals is proposed. By controlling the duty ratio D in the buck-boost mode, the proposed system can control the compensation voltage. For case verification of the proposed system, PSIM simulation is achieved. As a result, in case that the voltage sags-swells occur 10[%], 20[%], 60[%] in power distribution system, and, in case that the 50[%] under voltage sags-swells continuously occur, all case could compensate by the proposed system. Especially, the compensated voltage THD was examined under the condition of the 10[%]~50[%] voltage sags and the 20[${\Omega}$]~100[${\Omega}$] load changes. The compensated voltage THD was worse for the higher load resistances and more severe voltage sags. Finally, In case of the voltage swells compensation, the compensation factor has approached nearly 1 regardless of the load resistance changes, while the compensation factor of voltage sags was related to the load variations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.23-30
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• 2006

This paper presents a design of a high-efficiency CMOS DC-DC boost converter using a current-sensing feedback method. High-precision current-sensing circuity is incorporated in order to sense the current flowing in the inductor, which determines the switching scheme of the pulse-width modulation. The external components or large chip area for the frequency compensation can be avoided while maintaining the stable operations of the converter. Various input/output voltage levels can be available through the external resistor strings. The designed DC-DC converter is fabricated in a 0.18-um CMOS technology with a thick-gate oxide option. The converter shows the maximum efficiency over 90% for the output voltage of 3.3V and load current larger than 200mA. The load regulation is 1.15% for the load current change of 100mA.