• Journal of Convergence for Information Technology
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• v.11 no.2
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• pp.124-129
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• 2021

In this paper, an optimal controller design that guarantees absolute stability is proposed. The order of application of the thesis determines whether the delay time is included, and if the delay time is included, the delay time is approximated through the Pade approximation method. Then, the open loop transfer function for the process model and the controller transfer function is obtained, and the absolute stability interval is calculated by the Routh-Hurwitz discrimination method. In the last step, the optimal Proportional and Integral and Derivative(PID) control parameter value is calculated using a genetic algorithm using the interval obtained in the previous step. As a result, it was confirmed that the proposed method guarantees stability and is superior to the existing method in performance index by designing an optimal controller. If we study the compensation method for the delay time in the future, it is judged that better performance indicators will be obtained.

• The Korean Journal of Air & Space Law and Policy
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• v.25 no.2
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• pp.163-199
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• 2010

A frequent flyer program is a loyalty program offered by many airlines. Typically, airline customers enrolled in the program accumulate frequent flyer miles corresponding to the distance flown on that airline or its partners. There are other ways to accumulate miles. In recent years, more miles were awarded for using co-branded credit and debit cards than for air travel. Acquired miles can be redeemed for free air travel; for other goods or services, such as travel class upgrades, airport lounge access or priority bookings. The first modern frequent flyer program was created Texas International Airlines in 1979. This program was also adopted in Korean Air in 1984. Since then, the mileage programs have grown enormously. As of June 2009, the total member of two national airlines in Korea had been over thirty million. However, accumulated miles could be burden of airlines, because the korean corporations should record the annual financial report the accumulate mileage on a liability account by 'the international financial report standards(IFRS)' next year. The korean airlines need to minimize the accumulated miles, so that for instance Korean Airlines SKYPASS-miles expire 5 years after being earned. It means that miles earned on or after July 2008 will expire after five years if unredeemed. Thus, this paper attempt to analyze the unfairness of the mileage rules of korean airlines by examining a specific portion of the conditions relating to consumer protection, because many mileage users has difficulties using mileage programs and complained the amendment of the mileage rules. In conclusion, the contemporary mileage rules in Korea are rather unsatisfactory, because airlines is not only recognizing a mileage into a kind of benefit but also denying inheritance of mileage and the legal nature of mileage as a property right. It is necessary to amend relevant mileage rules in view of consumer protection, because air mileage is not simple benefit but a right of mileage user.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.4
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• pp.596-601
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• 2020

Silicon carbide is considered a potentially useful material for high-temperature electronic devices because of its large band gap energy and p-type or n-type conduction that can be controlled by impurity doping. Accordingly, the thermoelectric properties of -SiC powder prepared by refined diatomite were investigated for high value-added applications of natural diatomite. -SiC powder was synthesized by a carbothermal reduction of the SiO₂ in refined diatomite using carbon black. An acid-treatment process was then performed to eliminate the remaining impurities (Fe, Ca, etc.). n-Type semiconductors were fabricated by sintering the pressed powder at 2000℃ for 1~5h in an N2 atmosphere. The electrical conductivity increased with increasing sintering time, which might be due to an increase in carrier concentration and improvement in grain-to-grain connectivity. The carrier compensation effect caused by the remaining acceptor impurities (Al, etc.) in the obtained -SiC had a deleterious influence on the electrical conductivity. The absolute value of the Seebeck coefficient increased with increasing sintering time, which might be due to a decrease in the stacking fault density accompanied by grain or crystallite growth. On the other hand, the power factor, which reflects the thermoelectric conversion efficiency of the present work, was slightly lower than that of the porous SiC semiconductors fabricated by conventional high-purity -SiC powder, it can be stated that the thermoelectric properties could be improved further by precise control of an acid-treatment process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.12
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• pp.1350-1359
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• 2008

This paper presents a wideband doubly balanced resistive mixer fabricated using $0.5{\mu}m$ GaAs p-HEMT process. Three baluns are employed in the mixer. LO and RF baluns operating over an 8 to 20 GHz range were implemented with Marchand baluns. In order to reduce chip size, the Marchand baluns were realized by the meandering multicoupled line and inductor lines were inserted to compensate for the meandering effect. IF balun was implemented through a DC-coupled differential amplifier. The size of IF balun is $0.3{\times}0.5\;mm^2$ and the measured amplitude and phase unbalances were less than 1 dB and $5^{\circ}$, respectively from DC to 7 GHz. The mixer is $1.7{\times}1.8\;mm^2$ in size, has a conversion loss of 5 to 11 dB, and an output third order intercept(OIP3) of +10 to +15 dBm at 16 dBm LO power for the operating bandwidth.

• Culinary science and hospitality research
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• v.21 no.1
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• pp.15-29
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• 2015

The purpose of this study is to identify the effect of job satisfaction on job performance and to examine the moderating effects of employment type of the employees in franchised Korean restaurants. The questionnaire was distributed to the employees in Korean restaurants having abroad branches of the 300 distributed questionnaire, and 271 copies were used in the analysis by exploring factor analysis, reliability analysis, correlation analysis, multiple regression and hierarchical moderated regression analysis through SPSS ver. 18.0. The results of the study were as followed; First, job satisfaction, the work and superior factor have positive influence on job performance, but wages and promotion factor have negative influence. Second, the employment type has the partially moderating effects between job satisfaction and job performance with interactive term(superior$^*$ employment type). On the basis of these results, it is suggested that the company has fair criteria for evaluating systems and reward program to the employees regardless of employment type. This study has the limitations of simple variable and employment type.

• Journal of Korean Society of Forest Science
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• v.52 no.1
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• pp.37-49
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• 1981

The purpose of the study is to find out the objective method of valuation on the forest stands through the analysis of logging costs that is positively related to timber production. The two forest (Amgog, Whangryoung), located nereby, but forest type, logging and skidding conditions being slightly different, were slected to carry out the study. The objective timber stumpage value were determined by investigating the appropriate timber production costs and profits of logging operations. The main result obtained in this study are as follows: 1. The rate of logging cost in consisting of timber market price is 13.15% in the area of Amgog logging place and 19.48% in Whangryoung. 2. The rate of the other production cost excluding logging cost is 15.36% in the area of Amgog logging place and 28.85% in Whangryoung. 3. The total rate of timber production cost in consisting of the market price is more than 28.51% in the area of Amgog logging place and 48.33% in Whangryoung, 4. Though the productivity of forest land is affected by the selection of tree species, tending, treatments and effective management of forest land, the more important problem is improvement of logging condition. 5. The rate of production cost in timber price is so high that we should endeavore to improve the productivity of labour and its quality, and minimize the difference of piece work per day in accordance to the various site condition. 6. Although the profit of forest industry is related to the period of recapturing investment, it is more closely related to the working condition, risk of investment and continuous change of social investment interest. 7. If the right variables which are related to the timber market, are objectively obtained, the stumpage value of mature forests can be objectively caculated by applying straight line discounting method or compound discounting method in caculating the stump to market price.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.31-38
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• 2005

The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.