• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.7-14
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• 2005

This paper presents a new low power BIST TPG scheme. It uses a transition monitoring window (TMW) that is comprised of a transition monitoring window block and a MUX. When random test patterns are generated by an LFSR, transitions of those patterns satisfy pseudo-random gaussian distribution. The Proposed technique represses transitions of patterns using a k-value which is a standard that is obtained from the distribution of U to observe over transitive patterns causing high power dissipation in a scan chain. Experimental results show that the Proposed BIST TPG schemes can reduce scan transition by about $60\%$ without performance loss in ISCAS'89 benchmark circuits that have large number scan inputs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.46-56
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• 2002

In this paper, we describe a hardware-software co-verification methodology and environment in developing a mobile station modem chip for cdma2000 1x which is one of the 3rd generation mobile communication standards. By constructing an efficient co-verification environment for a register-transfer-level hardware model and a physical-layer software model combining a channel link simulator and a versatile test-bench, we can drastically reduce both time and cost for developing a complex three-million-gate class system integrated circuit.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.3-12
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• 2016

Recently, the study on 5G mobile communication systems using the millimeter-wave frequency band have been actively promoted and the importance of compensation of the nonlinearity of power amplifier caused by the characteristics of millimeter-wave frequency propagation attenuation is increasing. In the paper, we propose a piecewise polynomial model based on subdivision coefficient which are characteristics of power amplifier separated linear section and a non-linear section. In addition, the structure of digital predistortion based on the proposed model and direct learning method are proposed to implement a digital predistortion. To verify the proposed model, digital predistortion based on the proposed model and direct learning method for 60 GHz power amplifier using LTE signal implemented in the FPGA. And the hardware test bench measured performance and complexity. The proposed model achieves 3.3 dB gain over the single polynomial model in terms of the ACLR and reduces 7.5 percent in terms of the complexity.

• The Journal of the Korea Contents Association
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• v.10 no.3
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• pp.64-71
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• 2010

Recently, to achieve high performance of the processor, the cache is splits physically into two parts, one for instruction and one for data. This paper proposes an architecture of asynchronous instruction cache based on mixed-delay model that are DI(delay-insensitive) model for cache hit and Bundled delay model for cache miss. We synthesized the instruction cache at gate-level and constructed a test platform with 32-bit embedded processor EISC to evaluate performance. The cache communicates with the main memory and CPU using 4-phase hand-shake protocol. It has a 8-KB, 4-way set associative memory that employs Pseudo-LRU replacement algorithm. As the results, the designed cache shows 99% cache hit ratio and reduced latency to 68% tested on the platform with MI bench mark programs.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.41 no.10
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• pp.805-812
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• 2013

The operational flight program(OFP) which has the functions of I/O processing with avionics, flight control logic calculation, fault diagnosis and redundancy mode is embedded in the flight control computer of Smart UAV. The OFP was developed in the environment of PowerPC 755 processor and VxWorks 5.5 real-time operating system. The OFP consists of memory access module, device I/O signal processing module and flight control logic module, and each module was designed to hierarchical structure. Memory access and signal processing modules were verified from bench test, and flight control logic module was verified from hardware-in-the-loop simulation(HILS) test, ground integration test, tethered test and flight test. This paper describes development environment, software structure, verification and management method of the OFP.

• Journal of the Society of Naval Architects of Korea
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• v.34 no.3
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• pp.70-75
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• 1997

This paper concerns with a safe and efficient transportation method of hot-coils on cargo ship. An automatic loading and unloading system of hot-coils by cassettes, which secure the geometrically unstable cargo, hot-coil, by supporting with wedges on both sides, is considered efficient and profitable. Safety of hot-coil on cassette and subsequently safety of total cargo ship are directly affected by the wedge angle of cassette. For optimal design of the cassette wedge angle, a dynamic model of hot-coil/cassette cargo is developed with constraint of no relative motions between the coil and the cassette. Force equilibrium conditions between resultant alternating inertia forces on hot-coil due to motions of cargo ship in waves and reactions forces from cassette wedge surfaces are derived and consequently a numerical simulation code is implemented. Cassette wedge angle of 37 degree is taken as optimal by considering dynamic stability of hot-coil and strength of cassette structure. Performance of the designed cassette wedge angle is investigated by scaled bench test.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.12A
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• pp.1311-1319
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• 2007

This paper presents the VHDL implementation procedure of the passive RFID tag operating in Ultra High Frequency. The operation of the tag compatible with the EPCglobal Class1 Generation2(GEN2) protocol is verified by timing simulation after synthesis and implementation. Due to the reading range with relatively large distance, a passive tag needs digital processor which facilitates faster decoding, encoding and state transition for enhancement of an interrogation rate. In order to satisfy linking time, the pipe-line structure is used, which can minimize latency to serial input data stream. We also propose the sampling strategy to decode the Preamble, the Frame-sync and PIE symbols in reader commands. The simulation results with the fastest data rate and multi tags environment scenario show that the VHDL implemented tag performs faster operation than GEN2 proposed.

• Journal of the Korea Computer Graphics Society
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• v.22 no.5
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• pp.1-16
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• 2016

In this paper, we propose and efficient curve reconstruction method based on the classical least-square fitting scheme. Specifically, given planar sample points equipped with normals, we reconstruct the objective curve as the zero set of a hierarchical implicit ZP(Zwart-Powell)-spline that can recover large holes of dataset without loosing the fine details. As regularizers, we adopted two: a Tikhonov regularizer to reduce the singularity of the linear system and a discrete Laplacian operator to smooth out the isocurves. Benchmark tests with quantitative measurements are done and our method shows much better quality than polynomial methods. Compared with the hierarchical bi-quadratic spline for datasets with holes, our method results in compatible quality but with less than 90% computational overhead.

• The Transactions of the Korea Information Processing Society
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• v.2 no.5
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• pp.777-786
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• 1995

This paper describes several algorithms for technology mapping of logic functions into interesting and popular FPGAs that use look-up table memories. In order to improve the technology mapping for FPGA, some existing multi-level logic synthesis, decomposition reduction and packing techniques are analyzed and compared. And then new algorithms such as node-pair decomposition, merging fanin, unified reduction and multiple output decomposition which are used for combinational logic design, are proposed. The cost function is used to minimize the number of CLBs and edges of the network. The cost is a linear combination of each weight that is given by user. Finally we compare our new algorithm with previous logic design technique［8］. In an experimental comparison our algorithm requires 10% fewer CLB and nets than SIS-pga.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.62-70
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• 2007

In this paper, we design a mobile camera processor to support the MIPI CSI-2 and DPHY specification. The lane management sub-layer of CIS2 handles multi-lane configuration. Thus conceptually, the transmitter and receiver have each independent buffer on multi lanes. In the proposed architecture, the independent buffers are merged into a single common buffer. The single buffer architecture can flexibly manage data on multi lanes though the number of supported lanes are mismatched in a camera processor transmitter and a host processor. For a key issue for the data synchronization problem, the synchronization start codes are added as the starting for image data. We design synchronization logic to synchronize the received clock and to generate the byte clock. We present the verification results under proposed test bench. And we show the waves of simulation and logic synthesis results of the designed processor.