• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.7
• /
• pp.71-79
• /
• 2004

Packet-type data transmission is characterized by the continuous transmission of massive data with relatively constant rate. In such transmission, the dynamic power consumed on buses is influenced by the sequence of transmitted data. A new coding scheme called Sequence-Switch Coding (SSC) is proposed in this paper. SSC reduces the number of bus transitions in the transmission of packet-type data by changing the sending order of the data. Some simple algorithms are presented, In. The simulation results show that SSC outperforms the well-known Bus-Invert Coding with these algorithms. SSC is not a specific algerian but a method to reduce the number of bus-transitions. There could be lots of algorithms for realizing SSC. The variety of SSC algorithms provides circuit designers a wide range of trade-off between performance and circuit complexity.

• Proceedings of the Korean Institute Of Construction Engineering and Management
• /
• 2007.11a
• /
• pp.593-598
• /
• 2007

Most of people still use the bus, which is one of transportation. But the space of cauch station where the passengers wait for the bus is still not enough for them in effect. Therefore, the space is analyzed through looking into the behaviors occurred in the waiting space .So, this paper defines the a primary factor affecting environmental from the existing environment and experience behaviors occurred in the existing environment, and suggests design guideline based on data and information from the result when redesigning.

• The Journal of the Convergence on Culture Technology
• /
• v.9 no.5
• /
• pp.475-480
• /
• 2023

As the digital fashion show developed through the pandemic period, this study analyzed the literature on the digital fashion show and presented basic data for the design of the metaverse fashion show space. Through keyword analysis, the flow of research was identified, and implications for space design for the metabus fashion show were derived through analysis of space, models and avatars, lighting, and communication. Through keyword analysis, it was possible to understand the conversion process of digital fashion show research in the pandemic situation. Metaverse fashion shows can express stages, avatars, and costumes that are impossible in the real world, but require design considering expressiveness. In the metaverse space, communication can be thought of as a designer's value delivery, digital marketing, and communication with customers.

• Journal of KIISE:Computer Systems and Theory
• /
• v.32 no.11_12
• /
• pp.629-638
• /
• 2005

In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.12
• /
• pp.35-44
• /
• 2005

SoC(systnn-on-a-chip) requires high bandwidth system bus for performing multiple functions. Performance of the system is affected by bandwidth of the system bus. In this paper, for efficient management of the bus resource on a SoC platform, we present a latency model of the shared bus organized by multiple layers. Using the latency model, we can analyze latencies of the shared bus on a SoC. Moreover we evaluate a throughput of the bus and compare with needed throughput of the SoC platform including IPs such as MPEG or USB 2.0. And we can use the results as a criteria to find out an optimal bus architecture for the specific SoC design. For verifying accuracy of the proposed model, we compared the latencies with the simulation result from MaxSim tools. As the result of simulation, the accuracy of the IS model for a single layer and multiple layer are over $96\%\;and\;85\%$ respectively.

• Archives of design research
• /
• v.16 no.4
• /
• pp.405-412
• /
• 2003

This research investigated the preference factor which has an effect on the forms of bus stop shelter in order to grasp the visual preference factor, which is necessary for planning and designing of bus stop shelter centering around user, starting with the question of the research regarding that a shelter is preferred by what kind of factor when the environmental conditions are regular. This research examined the relation between visual preference and preference factor which has an effect on it with Multiple Regression Analysis after evaluating visual preference for shelter form by user as applying of scoring system of Interval Scale. The result of the factor analysis by visual evaluation for the form of bus stop shelter through the said research result will have an great effect on the design of bus stop shelter centering around its user. Therefore, this research result will give a knowledge which is necessary for the plan and the installation of bus stop shelter, and contributes to shelter design and bus stop promotion which can maximize the satisfaction of user. As well, concerning the management of bus stop facilities, it will give useful guidelines for planning strategically the shelter management centering around user. In particular, It is estimated that the preference factor analysis by visual evaluation of the mass transportation user in daily life will be the cardinal point for bus stop plan.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.12 s.354
• /
• pp.23-32
• /
• 2006

Fast and accurate power bus design (FAPUD) method for multi-layers high-speed digital boards is devised for the power supply network design tool for accurate and precise high speed board. FAPUD is constructed, based on two main algorithms of the PBEC (Path Based Equivalent Circuit) model and the network synthesis method. The PBEC model exploits simple arithmetic expressions of the lumped 1-D circuit model from the electrical parameters of a 2-D power distribution network. The circuit level design based on PBEC is carried with the proposed regional approach. The circuit level design directly calculates and determines the size of on-chip decoupling capacitors, the size and the location of off-chip decoupling capacitors, and the effective inductances of the package power bus. As a design output, a lumped circuit model and a pre-layout of the power bus including a whole decoupling capacitors are obtained after processing FAPUD. In the tuning procedure, the board re-optimization considering simultaneous switching noise (SSN) added by I/O switching can be carried out because the I/O switching effect on a power supply noise can be estimated over the operation frequency range with the lumped circuit model. Furthermore, if a design changes or needs to be tuned, FAPUD can modify design by replacing decoupling capacitors without consuming other design resources. Finally, FAPUD is accurate compared with conventional PEEC-based design tools, and its design time is 10 times faster than that of conventional PEEC-based design tools.

• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.20 no.3
• /
• pp.20-33
• /
• 2021

Modern society is steadily implementing policies to encourage public transportation to cope with the growing traffic demand on limited roads. The expectation is rising for transit signal priority to ensure the speed of buses as the installation of the bus rapid transit(BRT) expands nationwide to secure the competitiveness of buses. On the other hand, the form of BRT stops without considering some aspects of bus operation may increase the number of stops on the bus, thereby reducing the effectiveness of bus signal priority applications. This study suggests the type of bus stop to increase the operation efficiency of buses by analyzing the bus signal priority effect according to the BRT station type using Hannuri-daero, Sejong. The bus signal priority is used to maximize the two-way bandwidth of passenger cars and buses. As a result of the application, the effectiveness of the bus signal priority at the stop causing the double stop of the bus was reduced drastically, and the efficiency of the bus signal priority was increased significantly after improvement. These results are expected to be used as basic data in the form of proper bus stops considering the aspects of traffic operation when designing BRT stops in new towns in the future.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.6 s.360
• /
• pp.69-76
• /
• 2007

A new circuit design for Bus-Invert Coding is presented in this paper. The new scheme sends the coding information through the bus-lines instead of the invert-line which has been used conventionally for many types of Bus-Invert algorithms. By employing a newly developed bus-driver called Flip-Driver and a selection circuit, it not only removes the invert-line but suppresses the additional bus-transitions in sending coding information. It is verified by simulations that the efficiency of various Bus-Invert algorithms is increased about 40% to 100% by employing the new design.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.35 no.8
• /
• pp.863-867
• /
• 2011

In this paper, we analyze the characteristic test results of an MR damper for a cruise bus, and we model the nonlinear hysteretic characteristics of the damper using arctangent and polynomial functions. We establish an experimental model of the MR damper according to the input current, and we set the model parameters using the MATLAB Optimization Toolbox. The model is verified via a computer simulation of a full-car model.