• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.8
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• pp.1777-1781
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• 2011

Tosin backplane system design of this study (Backplane) from the HSTL (High-Speed Transceiver Logic) characteristics of the transmit and receive data using the HSPICE simulations and the actual implementation on the FPGA Data transmission characteristics were described by comparing the simulation results. Simulation and measurement criteria for point to point data transmission characteristics of wire length possible to send and receive data about the speed limits were reviewed. Measured point to point connection to send and receive signals at terminal velocity, the factors that affect the electrical noise around the wire length and showed a very important role.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.236-237
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• 2010

기존의 교류배전 시스템의 신재생 에너지원과의 연동 비용이성을 해결하고 전체 시스템의 효율을 높이기 위해 연구되고 있는 직류배전 시스템으로 전환하기 위해서는 옥내배선용 도선의 재검토가 필수적이다. 따라서 본 논문에서는 직류배전 전압 및 부하전류, 도선의 종류와 길이, 각종 규제사항 등을 고려하여 가정용 직류배전 시스템 적용에 적합한 도선 선정을 위한 가이드라인을 제시하고 이를 보급형 $100m^2$형 주택을 기준으로 한 시뮬레이션을 통해 타당성을 보인다.

• Korean Chemical Engineering Research
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• v.59 no.4
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• pp.632-638
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• 2021

With the copper interconnection in the semiconductor process, complex residues including copper oxide, fluoride, and polymeric fluorocarbon are formed by plasma etching. In this study, a cleaning solution was prepared with a component having an amine group (-NH₂) and a carboxyl group (-COOH), and the characteristics of removing post-etch residues in the copper wiring process were analyzed. In the cleaning solution containing an amine group, the length of the component substituted with nitrogen and the length of the carbon chain influenced the cleaning effect, and the etching rate of copper oxide increased as the pH of the cleaning solution increased. The activity of the amine group is in the basic region, and the activity of the carboxyl group is in the acidic region, and the cleaning process proceeds through complex formation with copper or copper oxide in each region.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2005.05a
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• pp.84-91
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• 2005

A study to assess and show applications of the easy lighting constructions of the new technics has presented in this paper. we have taken the present men-power to determine the optimum levels of the selected labour cost and analysis of the unit prices on the new developed lighting device for modularized to unit length, named Lite-way.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.55-67
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• 2010

The electrical properties of a back drilled via-hole (BDH) without the open-stub and the plated through via-hole (PTH) with the open-stub, which is called the conventional structure, in a high-count multi~layered (HCML) printed circuit board (PCB) were investigated for a high-speed digital system, and a selected inner layer to transmit a high-speed signal was farthest away from the side to mount the component. Within 10 GHz of the broadband frequency, a design of experiment (DOE) methodology was carried out with three cause factors of each via-hole structure, which were the distance between the via-holes, the dimensions of drilling pad and the anti-pad in the ground plane, and then the relation between cause and result factors which were the maximum return loss, the half-power frequency, and the minimum insertion loss was analyzed. Subsequently, the empirical formulae resulting in a macro model were extracted and compared with the experiment results. Even, out of the cause range, the calculated results obtained from the macro model can be also matched with the measured results within 5 % of the error.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.2
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• pp.146-156
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• 2002

In this paper, a new virtual-straight line parameter determination methodology and fast time domain simulation technique for non-uniform interconnects are presented and verified. Time domain signal response of interconnects circuit considering the characteristic of non-linear transistor is performed by using model order reduction method. Since model order reduction method is peformed by using per unit length parameters, virtual- straight line parameters for non-uniform interconnects are determined. Its method is integrated into Berkeley SPICE and shown that time domain signal responses using proposed method have a good agreement with the results of conventional circuit simulator HSPICE. The proposed method can be efficiently employed in the high-performance VLSI circuit design since it can provide a fast and accurate time domain signal response of complicated multi - layer interconnects.

• Journal of the Korean Vacuum Society
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• v.17 no.2
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• pp.109-112
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• 2008

The miniaturization of device size and submicron process causes serious problems in conventional metallization due to the solubility of silicon and metal at the interface, such as an increasing contact resistance in the contact hole and interdiffusion between metal and silicon. Moreover, the interaction between Cu and Si is so strong and detrimental to the electrical performance of Si even at temperatures below $200^{\circ}C$. Therefore it is necessary to implement a barrier layer between Cu and Si. So we study W-C-N diffusion barrier for prevent Cu diffusion as a function of $N_2$ gas flow and thermal stability. Especially, we also study the W-C-N diffusion barrier for analyzing the change of lattice constants.

• Journal of IKEEE
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• v.25 no.4
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• pp.591-597
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• 2021

This paper proposes an EMC-aware PCB design method to reduce electromagnetic emission, where trace length and teturn path of critical signal are shortened by changing chip location and trace layout on the PCB, while additional filters or decoupling capacitors are not required. In the proposed method, signal velocity is calculated for various signals on the PCB. Critical signal with the fastest signal velocity is determined and its return path is shortened as much as possible by placing chip location and trace routing first. Return path of critical signal should be carefully designed not to have discontinuity. Power plane and ground plane should be carefully designed not to be divided, since these planes are the reference of return path. The proposed method was applied to automotive directional Bluetooth speaker which failed to pass CISPR 32 and CISPR 25 EMC tests. Its PCB was redesigned based on the proposed method and it easily passed the EMC tests. The proposed method is useful to EMC-sensitive electronic equipments.

• Journal of the Korean Vacuum Society
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• v.17 no.6
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• pp.518-522
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• 2008

The miniaturization of device size and multilevel interlayers have been developed by ULSI circuit devices. These submicron processes cause serious problems in conventional metallization due to the solubility of silicon and metal at the interface, such as an increasing contact resistance in the contact hole and interdiffusion between metal and silicon. Therefore it is necessary to implement a barrier layer between Si and metal. Thus, the size of multilevel interconnection of ULSI devices is critical metallization schemes, and it is necessary reduce the RC time delay for device speed performance. So it is tendency to study the Cu metallization for interconnect of semiconductor processes. However, at the submicron process the interaction between Si and Cu is so strong and detrimental to the electrical performance of Si even at temperatures below $200^{\circ}C$. Thus, we suggest the tungsten-carbon-nitrogen (W-C-N) thin film for Cu diffusion barrier characterized by nano scale indentation system. Nano-indentation system was proposed as an in-situ and nanometer-order local stress analysis technique.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.12
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• pp.616-619
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• 2004

Electrical circuits with semiconductor are very weak against lightning surge. The surge protective devices for electronic circuit and AC power lines are becoming more widely used. To achieve effective method of surge protection, there are needs for correlation between lightning surge and indoor wire length or installation height of indoor wire. The aim of this present work is to investigate the propagation characteristics of lightning surge according to variation of wire length. As a consequence, the maximum voltage at the end of the open wire in proportion to length of indoor wire. Therefore this result may be raw data for establishment of surge protection system.