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(Signal Integrity Verification of a General VLSI Interconnects using Virtual-Straight Line Model)  

Jin, U-Jin (Dept. of Electronic computer Engineering, Hanyang University)
Eo, Yeong-Seon (Dept. of Electronic computer Engineering, Hanyang University)
Sim, Jong-In (Dept. of Electronic computer Engineering, Hanyang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.39, no.2, 2002 , pp. 146-156 More about this Journal
Abstract
In this paper, a new virtual-straight line parameter determination methodology and fast time domain simulation technique for non-uniform interconnects are presented and verified. Time domain signal response of interconnects circuit considering the characteristic of non-linear transistor is performed by using model order reduction method. Since model order reduction method is peformed by using per unit length parameters, virtual- straight line parameters for non-uniform interconnects are determined. Its method is integrated into Berkeley SPICE and shown that time domain signal responses using proposed method have a good agreement with the results of conventional circuit simulator HSPICE. The proposed method can be efficiently employed in the high-performance VLSI circuit design since it can provide a fast and accurate time domain signal response of complicated multi - layer interconnects.
Keywords
Interconnects; silicon substrate effect; shielding effect; virtual-straight line model; signal integrity.;
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1 U. Ushiku, H. Kushibe, and H. Ono, 'Design Guide Line for Deep Sub-Micrometer Interconnections,' IEEE Proceedings of the 1990 VMIC., pp. 413-415, 1990
2 The National Technology Roadmap Semiconductor Technology Needs, SIA Report, 1997
3 H. B. Bakoglu, 'Interconnect for the 90s : System Level Electronic Issues,' IEDM 1992 Short Course : Interconnect for the 90s, San Jose, CA, 1992
4 T. Sakurai, 'Closed-Form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSI's,' IEEE Trans. ED., vol. 40, No. 1, pp. 118-124, Jan. 1993   DOI   ScienceOn
5 Y. Eo and W. R. Eisenstadt, 'High-Speed VLSI Interconnect Modeling Based on S-Parameter Measurements,' IEEE Trans. CPMT, vol. 16, No. 5, pp. 555-562, Aug. 1993   DOI   ScienceOn
6 H. Hasegawa, M. Furukawa, and H. Yanai, 'Properties of Microstrip Line on $Si-SiO_2$ System,' IEEE Trans. MTT., vol. MTT-19, No. 11, pp 869-881, Nov. 1971
7 K. W. Goossen and R. B. Hammond, 'Modeling of Picosecond Pulse Propagation in Microstrip Interconnections on Integrated Circuits,' IEEE Trans. MTT., vol. 37, No. 3, pp. 469-478, Mar. 1989   DOI   ScienceOn
8 W. T. Weeks, 'Calculation of Coefficients of Capacitance of Multiconductor Transmission Lines in the Presence of a Dielectric Interface,' IEEE Trans. MTT., vol. MTT-18, No. 1, pp. 35-43, Jan. 1970
9 H. A. Wheeler, 'Transmission-Line Properties of a Strip on a Dielectric Sheet on a Plane,' IEEE Trans. MTT, vol. MTT-25, no. 8, pp. 631-647, Aug. 1977
10 J-H. Chern, J. Huang, L. Arledge, P-C. Li, and P. Yang, 'Multilevel Metal Capacitance Model for CAD Design Synthesis Systems,' IEEE EDL., vol. 13, No. 1, pp. 32-34, Jan. 1992   DOI   ScienceOn
11 R. Gupta, B. Tutuianu, and L. T. Pileggi, 'The Elmore Delayas a Bound for RC Trees with Generalized Input Signals,' IEEE Trans. CAD, vol. 16, No. 1, pp. 95-104, Jan. 1997   DOI
12 D. Sylvester, J. C. Chen, and C. Hu, 'Investigation of Interconnect Capacitance Characterization Using Charge-Based Capacitance Measurement(CBCM) Technique and Three-Dimensional Simulation,' IEEE JSSC, vol. 33, No. 13, pp. 449-453, Mar. 1998   DOI   ScienceOn
13 J. C. Chen, D. Sylvester, and C. Hu, 'An On-Chip, Interconnect Capacitance Characterization Method with Sub-Femto-Farad Resolution,' IEEE Trans. SM., vol. 11, No. 2, pp. 204-209, May 1998   DOI   ScienceOn
14 L. T. Pillage and R. A. Rohrer, 'Asymptotic Waveform Evaluation for Timing Analysis,' IEEE Trans. CAD, vol. 9, no. 4, pp. 352-366, Apr. 1990   DOI   ScienceOn
15 S. Lin and E. S. Kuh, 'Transient Simulation of Lossy Interconnects Based on the Recursive Convolution Formulation,' IEEE Trans. CAS., vol. 39, no. 11, pp. 879-892, Nov. 1992   DOI
16 R. Gupta, B. Krauter, and L. T. Pileggi, 'Transmission Line Synthesis via Constrained Multivariable Optimization,' IEEE Trans. CAD, vol. 16, No. 1, pp. 6-19, Jan. 1997   DOI   ScienceOn
17 MAXWELL 3D Parameter Extractor User's Reference, Pittsburgh, TA : Ansoft, 1994
18 Q. Yu and E. S. Kuh, 'Exact Moment Matching Model of Delay Transmission Lines and Application to Interconnect Delay Estimation,' IEEE Trans. VLSI Systems, vol. 3, no. 2, pp. 311-322, Jun. 1995   DOI   ScienceOn
19 C. Wei, R. H. Harrington, J. R. Mautz, and T. K. Sarkar, 'Multiconductor transmission Lines in Multilayered Dielectric Media,' IEEE Trans. MTT, vol. 32, no. 4, pp. 439-450, Apr. 1984   DOI   ScienceOn
20 P. J. Van Wijnen, H. R. Claessen, and E. A. Wolsheimer, 'A New Straightforward Calibration and Correction Procedure for on wafer High Frequency S-Parameter Measurements (45MHz-18GHz),' IEEE Proceedings of the 1987 BCTM., pp. 70-73, 1987
21 A. E. Ruehli and P. A. Brennan, 'Capacitance Models for Integrated Circuit Metalization Wires,' IEEE JSSC., vol. sc-10, No. 6, pp. 530-536, Dec. 1975
22 M. Sadiku, Numerical Techniques in Electromagetics, CRC press, 1992
23 Y. Kim, Y. Park, Y. Eo et al., 'Simulator for interconnects and general multilane analysis (SIGMA) : Simulation algorithm of lossy multiple transmission lines,' J. of Kor. Phys. Society, vol. 33, pp. 129-134, Nov. 1998