• Journal of Advanced Navigation Technology
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• v.28 no.1
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• pp.129-135
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• 2024

In this paper, an analytical approach for the design and analysis of an aperiodic electromagnetic bandgap (EBG)-based power distribution network (PDN) in high-speed integrated-circuit (IC) packages and printed circuit boards (PCBs) is proposed. Aperiodic EBG is an effective method to solve the noise problem of high-speed IC packages and PCBs. However, its analysis becomes challenging due to increased computation time. To overcome the problem, the proposed analytical method entails deriving impedance parameters for EBG island and the overall PDN, which includes locally placed EBG structures. To validate the proposed method, a test vehicle is fabricated, demonstrating good agreement with the measurements. Significantly, the proposed analytical method reduces computation time by 99.7 %compared to the full-wave simulation method.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.10
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• pp.5906-5911
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• 2014

Currently, there are many processes of package assembly and inspections of real fields that examine whether a manufactured semiconductor can be operated regularly and can endure low humidity or high temperatures. As the inspection equipment of a semiconductor test handler picker has been used at the inspection process, these inspection equipment frames were modelled in 3D and these models were analyzed using 3 kinds of fatigue loadings. As the analysis result, maximum deformation occurred at the midparts of the frames at cases 1 and 2. Among the cases of nonuniform fatigue loads, the 'SAE bracket history' with the severest change in load became the most unstable but the 'Sample history' became the most stable. Fatigue analysis result can be used effectively with the design of an inspecting equipment frame of a semiconductor test handler picker to examine the prevention and durability against damage.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.1
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• pp.31-39
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• 2014

For mobile application, semiconductor packages are increasingly moving toward high density, miniaturization, lighter and multi-functions. Typical wafer level packages (WLP) is fan-in design, it can not meet high I/O requirement. The fan-out wafer level packages (FOWLPs) with reconfiguration technology have recently emerged as a new WLP technology. In FOWLP, warpage is one of the most critical issues since the thickness of FOWLP is thinner than traditional IC package and warpage of WLP is much larger than the die level package. Warpage affects the throughput and yield of the next manufacturing process as well as wafer handling and fabrication processability. In this study, we investigated the characteristics of warpage and main parameters which affect the warpage deformation of FOWLP using the finite element numerical simulation. In order to minimize the warpage, the characteristics of warpage for various epoxy mold compounds (EMCs) and carrier materials are investigated, and DOE optimization is also performed. In particular, warpage after EMC molding and after carrier detachment process were analyzed respectively. The simulation results indicate that the most influential factor on warpage is CTE of EMC after molding process. EMC material of low CTE and high Tg (glass transition temperature) will reduce the warpage. For carrier material, Alloy42 shows the lowest warpage. Therefore, considering the cost, oxidation and thermal conductivity, Alloy42 or SUS304 is recommend for a carrier material.

• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.8
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• pp.2139-2157
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• 1994

In order to understand the delamination between leadframe and epoxy molding compound in an electronic packaging of surface mounting type, the stress intensity factor, T-stress and J-integral in fracture mechanics are obtained. The effects of geometry, material properties and molding process temperature on the delamination are investigated taking into account the temperature dependence of the material properties, which simulates as more realistic condition. As the crack length increases the J-integral increases, which suggest that the crack propagates if it starts growing from the small size. The effects of the material properties and molding process temperature on stress intensity factor, T-stress is and J-integral are less significant than the chip size for the practical cases considered here. The T-stress is negative in all eases, which is in agreement with observation that interfacial crack is not kinked until the crack approaches the edge of the leadframe.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.19-25
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• 2011

The size reduction of the semiconductor chip and the improvement of the electrical performance have been enabled through the introduction of the Cu/Low-K process in modern electronic industries. However, Cu/Low-K has a disadvantage of the physical properties that is weaker than materials used for existing semiconductor manufacture process. It causes many problems in chip manufacturing and package processes. Especially, the delamination between the Cu layer and the low-K dielectric layer is a main defect after the temperature cycles. Since the Cu/Low-K layer is located on the top of the pad of the flip chip, the stress on the flip chip affects the Cu/Low-K layer directly. Therefore, it is needed to improve the underfill process or materials. Especially, it becomes very important to select the underfill to decrease the stress at the flip-chip and to protect the solder bump. We have solved the delamination problem in a 90 nm Cu/Low-K flip-chip package after the temperature cycle by selecting an appropriate underfill.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.89-93
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• 2018

Ceramic substrates applied to power modules of electric vehicles are required to have properties of high thermal conductivity, high electrical insulation, low thermal expansion coefficient and resistance to abrupt temperature change due to high power applied by driving power. Aluminum nitride and silicon nitride, which are applied to heat dissipation, are considered as materials meeting their needs. Therefore, in this paper, the properties of aluminum nitride and silicon nitride as radiator plate materials were compared through a commercial analysis program. As a result, when the process of applying heat of the same condition to aluminum nitride was implemented by simulation, the silicon nitride exhibited superior impact resistance and stress resistance due to less stress and warping. In terms of thermal conductivity, aluminum nitride has superior properties as a heat dissipation material, but silicon nitride is more dominant in terms of reliability.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.4
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• pp.50-60
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• 2023

Ball Grid Array (BGA) is a widely used package type due to its high pin density and good heat dissipation. In BGA, solder balls play an important role in electrically connecting the package to the PCB. Therefore, understanding the inelastic deformation of solder balls under various mechanical loads is essential for the robust design of semiconductor packages. In this study, the geometrical effect on the inelastic deformation and fracture of solder balls were analyzed by finite element analysis. The results showed that fracture occurred in both tilted and hourglass shapes under shear loading, and no fracture occurred in all cases under compressive loading. However, when bending was applied, only the tilted shape failed. When shear and bending loads were combined with compression, the stress triaxiality was maintained at a value less than zero and failure was suppressed. Furthermore, a comparison using the Lagrangian-Green strain tensor of the critical element showed that even under the same loading conditions, there was a significant difference in deformation depending on the shape of the solder ball.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.37-44
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• 2013

It is well known that thermal deformation of electronic packages with Pb-Sn solder and with lead-free solder is significantly affected by material properties consisting the package, as well as those of the solder itself. In this paper, the method for determining coefficient of thermal expansion(CTE) of new material is established by using temperature characteristic of strain gages, and the CTE of molding compound are obtained experimentally. The temperature-dependent CTE of molding compound for Pb-Sn solder and that for lead-free solder are obtained by using strain measurements with well known steel specimen and aluminium specimen as reference specimens, and the CTE's are also measured non-contactly by using moire interferometry. Those results are compared, and the agreement between the two types of strain gage experiment and the moire experiment show the strain gage method used in this paper to be reliable. In the case of the molding compound for Pb-Sn solder, the CTE is measured as approximately $15.8ppm/^{\circ}C$ regardless of the temperature. In the case for the lead-free solder, the CTE is measured as of approximately $9.9ppm/^{\circ}C$ below the temperature of $100^{\circ}C$, and then the CTE is increased sharply depending on the temperature, and reaches to $15.0ppm/^{\circ}C$ at $130^{\circ}C$.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.1
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• pp.69-73
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• 2010

Finite-element analyses were conducted to investigate the thermal stress in 3-dimensional stacked wafers package containing through-silicon-via (TSV), which is being widely used for 3-Dimensional integration. With finite element method (FEM), thermal stress was analyzed with the variation of TSV diameter, bonding diameter, pitch and TSV height. It was revealed that the maximum von Mises stresses occurred at the edge of top interface between Cu TSV and Si and the Si to Si bonding site. As TSV diameter increased, the von Mises stress at the edge of TSV increased. As bonding diameter increased, the von Mises stress at Si to Si bonding site increased. As pitch increased, the von Mises stress at Si to Si bonding site increased. The TSV height did not affect the von Mises stress. Therefore, it is expected that smaller Cu TSV diameter and pitch will ensure mechanical reliability because of the smaller chance of plastic deformation and crack initiation.

• Journal of the Semiconductor & Display Technology
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• v.15 no.4
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• pp.1-9
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• 2016

The warpage on mobile phone camera packages occurs due to the CTE(Coefficient of Thermal Expansion) mismatch between a thin silicon die and a substrate. The warpage in the optical instruments such as camera module has an effect on the field curvature, which is one of the factors degrading the optical performance and the product yield. In this paper, we studied the effect of die bonding epoxy on the package and optical performance of mobile phone camera packages. We calculated the warpages of camera module packages by using a finite element analysis, and their shapes were in good agreement showing parabolic curvature. We also measured the warpages and through-focus MTF of camera module specimens with experiments. The warpage was improved on an epoxy with low elastic modulus at both finite element analysis and experiment results, and the MTF performance increased accordingly. The results show that die bonding epoxy affects the warpage generated on the image sensor during the packaging process, and this warpage eventually affects the optical performance associated with the field curvature.