• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.10-21
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• 1999

This paper describes a 12bit CMOS current cell matrix D/A converter which shows a conversion rate of 65MHz and a power supply of 3.3V. Designed D/A converter utilizes current cell matrix structure with good monotonicity characteristic and fast settling time, and it is implemented by using the tree structure bias circuit, the symmetrical routing method with ground line and the cascode current switch to reduce the errors of the conventional D/A converter caused by a threshold voltage mismatch of current cells and a voltage drop of the ground line. The designed D/A converter was implemented with a $0.6{\mu}m$ CMOS n-well technology. The measured data shows a settling time of 20ns, a conversion rate of 50 MHz and a power dissipation of 35.6mW with a single power supply of 3.3V. The experimental SNR, DNL, and INL of the D/A converter is measured to be 55dB, ${\pm}0.5LSB$, and ${\pm}2LSB$, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.348-354
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• 2009

It has analyzed that the device degradation by NBTI (Negative Bias Temperature Instability) stress induced the increase of gate-induced-drain-leakage(GIDL) current for p-MOSFETs. It is shown that the degradation magnitude, as well as its time, temperature, and field dependence, is govern by interface traps density at the silicon/oxide interface. from the relation between the variation of threshold voltage and subthreshold slope, it has been found that the dominant mechanism for device degradation is the interface state generation. From the GIDL measurement results, we confined that the EHP generation in interface state due to NBTI stress led to the increase of GIDL current. Therefore, one should take care of the increased GIDL current after NBTI stress in the ultra-thin gate oxide device. Also, the simultaneous consideration of reliability characteristics and dc device performance is highly necessary in the stress engineering of nanoscale CMOSFETs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1A
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• pp.80-86
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• 2010

This work has been measured and analyzed the device degradation of NBTI (Negative Bias Temperature Instability) stress induced the increase of gate-induced-drain-leakage(GIDL) current for p-MOS transistors of gate channel length 0.13 [${\mu}m$]. From the relation between the variation of threshold voltage and subthreshold slop by NBTI stress, it has been found that the dominant mechanism for device degradation is the interface state generation. From the GIDL measurement results, we confined that the EHP generation in interface state due to NBTI stress led to the increase of GIDL current. As a results, one should take care of the increased GIDL current after NBTI stress in the ultra-thin gate oxide device. Also, the simultaneous consideration of reliability characteristics and dc device performance is highly necessary in the stress parameters of nanoscale CMOS communication circuit design.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.1-8
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• 2013

This paper presents a variable gain amplifier(VGA) without passive devices. This VGA employes the architecture of current feedback amplifier and variable gain can be achieved by using the GM ratios of two trans-conductance(gm) circuits. To obtain linearity and high gain, it uses current division technique and source degeneration in feedback GM circuits. Input trans-conductance(GM) circuit was biased by using a tunable voltage controller to obtain variable gain. The prototype of the VGA is designed in $0.35{\mu}m$ CMOS technology and it is operating in sub-threshold region for low power consumption. The the gain of proposed VGA is varied from 23dB to 43dB, and current consumption is $2.82{\mu}A{\sim}3{\mu}A$ at 3.3V. The area of VGA is 1$120{\mu}m{\times}100{\mu}m$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.359-369
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• 2020

In this paper, we proposed a charge pump (CP) circuit that has a wide operating range while reducing the current mismatch for the PLL that generates the main clock of the CMOS X-Ray detector. The operating range and current mismatch of the CP circuit are determined by the characteristics of the current source circuit for the CP circuit. The proposed CP circuit is implemented with a wide operating current mirror bias circuit to secure a wide operating range and a cascode structure with a large output resistance to reduce current mismatch. The proposed wide operating range cascode CP circuit was fabricated as a chip using a 350nm CMOS process, and current matching characteristics were measured using a source measurement unit. At this time, the power supply voltage was 3.3 V and the CP circuit current ICP = 100 ㎂. The operating range of the proposed CP circuit is △VO_Swing=2.7V, and the maximum current mismatch is 5.15 % and the maximum current deviation is 2.64 %. The proposed CP circuit has low current mismatch characteristics and can cope with a wide frequency range, so it can be applied to systems requiring various clock speed.

• Journal of the Korean Magnetics Society
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• v.10 no.5
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• pp.196-202
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• 2000

Top synthetic spin valves with structure Ta/NiFe/CoFe/Cu/CoFe(P1)/Ru/CoFe(P2)/FeMn/Ta on Si(100) substrate with natural oxide were prepared by dc magnetron sputtering system, and investigated on the magnetoresistance properties and effective exchange bias field. As the thickness of FeMn increased above 150 $\AA$, MR ratio was decreased due to the current shunting effect. As the thickness of free layer decreased below 40$\AA$, MR ratio was reduced rapidly. In case of 40 $\AA$ thick of free layer, spin valve film with a structure Si(100)/Ta(50 $\AA$)/NiFe(27 $\AA$)/CoFe(13 $\AA$)/Cu(26 $\AA$)/CoFe(30 $\AA$)/Ru(7 $\AA$)/CoFe(15 $\AA$)/FeMn(100 $\AA$)/Ta(50 $\AA$) exhibited maximum MR ratio of 7.5 % and an effective exchange bias field of 600 Oe, respectively. Thickness difference dependence in this synthetic spin valve structure on effective exchange field was investigated and interpreted by the analytical method. It should be noted that thickness increase of CoFe(P 1) and decrease of CoFe(P2) in synthetic antiferromagnet leaded to the decrease in effective exchange bias field by experimentally and analytically.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.33-38
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• 2017

In this paper, a 4-channel common-cathode VCSEL diode driver array with 3.125 Gb/s per channel operation speed is realized. In order to achieve faster speed of the switching main driver with relatively large transistors, the transmitter array chip consists of a pre-amplifier with active inductor stage and also an input buffer with modified equalizer, which leads to bandwidth extension and reduced current consumption. The utilized VCSEL diode provides inherently 2.2 V forward bias voltage, $50{\Omega}$ resistance, and 850 fF capacitance. In addition, the main driver based upon current steering technique is designed, so that two individual current sources can provide bias currents of 3.0 mA and modulation currents of 3.3 mA to VCSEL diodes. The proposed 4-channel VCSEL driver array has been implemented by using a $0.11-{\mu}m$ CMOS technology, and the chip core occupies the area of $0.15{\times}0.18{\mu}m^2$ and dissipates 22.3 mW per channel.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.8-13
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• 2008

Noise in homogeneous extrinsic semiconductor samples is calculated due to distributed diffusion noise sources. As the length of the device shrinks at a fixed bias voltage, the ac-wise short-circuit noise current shows excess noise as well as thermal noise spectra. This excess noise behaves like a full shot noise when the channel length becomes very small compared with the extrinsic Debye length. For the first time, the analytic formula of the excess noise in extrinsic semiconductors from velocity-fluctuation noise sources is given for finite frequencies. This formula shows the interplay between transit time, dielectric relaxation time, and velocity relaxation time in determining the terminal noise current as well as the carrier density fluctuation. As frequency increases, the power spectral density of the excess noise rolls off. This formula sheds light on noise in nanoscale MOSFETs where quasi-ballistic transport plays an important role in carrier transport and noise.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1379-1385
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• 2009

We propose a low-power and high-speed client receiver for a mobile display digital interface (MDDI) newly in this paper. The low-power receiver is designed such that bias currents, sink and source currents, are insensitive to variations of power supply, process, temperature, and common-mode input voltage (VCM) and is able to operate at a rate of 450Mbps or above under the conditions of a power supply range of 3.0 to 3.6Vand a temperature range of -40 to 85$^{\circ}$C. And it is confirmed by a simulation result that the current dissipation is less than 500${\mu}$A. A test chip is manufactured with the Magna chip 0.35${\mu}$m CMOS process. When a test was done, the data receiver and data recovery circuits are functioning normally.

• Journal of Advanced Marine Engineering and Technology
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• v.30 no.8
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• pp.901-906
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• 2006

In this paper, the power amplifier using active bias circuits for LDMOS(Lateral Diffused Metal Oxide Semiconductor) MRF-21180 is designed and fabricated. According to change the temperature, the gate voltage of LDMOS is controlled by the fabricated active bias circuits which is made of PNP transistor to suppress drain current. The driving amplifier using MRF-21125 and MRF-21060 is made to drive the LDMOS MRF-21180 power amplifier. The variation of current consumption in the fabricated 60 watt power amplifier has an excellent characteristics of less than 0.1 A, whereas a passive biasing circuit dissipates more than 0.5 A. The implemented power amplifier has the gain over 9 dB, the gain flatness of less than $\pm$0.1 dB and input and output return loss of less than -6 dB over the frequency range 2.11 $\sim$ 2.17 GHz. The DC operation point of this power amplifier at temperature variation 0 $^{\circ}C$ to 60 $^{\circ}C$ is fixed by active bias circuit.