• Title/Summary/Keyword: 모드 변환

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A 2.4-GHz Dual-Mode CMOS Power Amplifier with a Bypass Structure Using Three-Port Transformer to Improve Efficiency (3-포드 변압기를 이용한 바이패스 구조를 적용하여 효율이 개선된 이중 모드 2.4-GHz CMOS 전력 증폭기)

  • Jang, Joseph;Yoo, Jinho;Lee, Milim;Park, Changkun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.23 no.6
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    • pp.719-725
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    • 2019
  • We propose a 2.4-GHz CMOS power amplifier (PA) with a bypass structure to improve the power-added efficiency (PAE) in the low-power region. The primary winding of the output transformer is split into two parts. One of the primary windings is connected to the output of the power stage for high-power mode. The other primary winding is connected to the output of the driver stage for low-power mode. Operation of the high power mode is similar to conventional PAs. On the other hand, the output power of the driver stage becomes the output power of the overall PA in the low power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. We designed the CMOS PA using a 180-nm RFCMOS process. The measured maximum output power is 27.78 dBm with a PAE of 20.5%. At a measured output power of 16 dBm, the PAE is improved from 2.5% to 12.7%.

A Numerical Study on Improvement in Seismic Performance of Nuclear Components by Applying Dynamic Absorber (동흡진기 적용을 통한 원전기기의 내진성능향상에 관한 수치적 연구)

  • Kwag, Shinyoung;Kwak, Jinsung;Lee, Hwanho;Oh, Jinho;Koo, Gyeong-Hoi
    • Journal of the Computational Structural Engineering Institute of Korea
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    • v.32 no.1
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    • pp.17-27
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    • 2019
  • In this paper, we study the applicability of Tuned Mass Damper(TMD) to improve seismic performance of piping system under earthquake loading. For this purpose, a mode analysis of the target pipeline is performed, and TMD installation locations are selected as important modes with relatively large mass participation ratio in each direction. In order to design the TMD at selected positions, each corresponding mode is replaced with a SDOF damped model, and accordingly the corresponding pipeline is converted into a 2-DOF system by considering the TMD as a SDOF damped model. Then, optimal design values of the TMD, which can minimize the dynamic amplification factor of the transformed 2-DOF system, are derived through GA optimization method. The proposed TMD design values are applied to the pipeline numerical model to analyze seismic performance with and without TMD installation. As a result of numerical analyses, it is confirmed that the directional acceleration responses, the maximum normal stresses and directional reaction forces of the pipeline system are reduced, quite a lot. The results of this study are expected to be used as basic information with respect to the improvement of the seismic performance of the piping system in the future.

Fabrication of 3-Step Light Transmittance-variable Smart Windows based on λ/2 Retardation Film (λ/2 Retardation Film을 이용한 3단계 투과율 가변 스마트윈도우 제작)

  • Il-Gu Kim;Ho-Chang Yang;Young-Min Park;Yo-Han Suh;Young Kyu Hong;Seung Hyun Lee
    • Journal of the Microelectronics and Packaging Society
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    • v.30 no.3
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    • pp.78-82
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    • 2023
  • A fabrication of smart windows with controllable visible light transmittance in three steps by using λ/2 retardation films based on a reactive mesogen (RM) material and polarizing films is demonstrated. The phase retardation films with a Δn·d value of λ/2 (λ: wavelength) convert the direction of a traveling light to the optical axis of the film symmetrically. In this work, the retardation characteristics according to the RM thickness were evaluated and henceλ/2 phase retardation film can be fabricated. The phase retardation film with Δn·d of 276.1 nm, which is close to λ/2 (=275 nm @550 nm), was fabricated. The light transmittance of a smart window with the structure of (polarizing film)/(glass)/(alignment layer)/(λ/2 retardation film) was measured in the transmission mode, half mode and blocking mode. The evaluation results show that the transmittance of the smart window can be controlled in three steps with 35.8%, 27.8%, and 18.2% at each mode, respectively. In addition, by fabricating a smart window with a size of 15×200 mm2, the feasibility of use in various fields such as buildings and automobiles was verified.

A Study on the Design of DC Parameter Test System (DC 파라메터 검사 시스템 설계에 관한 연구)

  • 신한중;김준식
    • Journal of the Institute of Convergence Signal Processing
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    • v.4 no.2
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    • pp.61-69
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    • 2003
  • In this paper, we developed the U parameter test system which inspects the property of DC parameter for semiconductor products. The developed system is interfaced by IBM-PC. It is consisted of CPLD part, ADC (Analogue to Digital Converter), DAC (Digital to Analogue Converter), voltage/current source, variable resistor and measurement part. In the proposed system, we have designed the constant voltage source and the constant current source in a part. The CPLD part is designed by VHBL, which it generates the control and converts the serial data to parallel data. The proposed system has two test channels and it operates VFCS mode and CFVS mode. The range of test voltage is from 0[V] to 100[V], and the range of test current is from 0[mA] to 100[mA)]. The diode is tested. The test results have a good performance.

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A Design of Sign-magnitude based Multi-mode LDPC Decoder for WiMAX (Sign-magnitude 수체계 기반의 WiMAX용 다중모드 LDPC 복호기 설계)

  • Seo, Jin-Ho;Park, Hae-Won;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.11
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    • pp.2465-2473
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    • 2011
  • This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems including WiMAX and WLAN. A new design of DFU based on sign-magnitude arithmetic instead of two's complement arithmetic is proposed, resulting in 18% reduction of gate count for 96 DFUs array used in mobile WiMAX LDPC decoder. A multi-mode LDPC decoder for mobile WiMAX standard is designed using the proposed DFU. The LDPC decoder synthesized using a 0.18-${\mu}m$ CMOS cell library with 50 MHz clock has 268,870 gates and 71,424 bits RAM, and it is verified by FPGA implementation.

Fabrication of the Corrugated Feed Horn for 85~115GHz Radio Telescope System (85~115GHz 전파망원경용 컬러게이트 급전 혼 제작)

  • Son, Tae-Ho;Han, Seog-Tae
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.19 no.6
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    • pp.640-646
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    • 2008
  • Design procedure of corrugated horn antenna for the mm-wave frequency range is presented, and hybrid condition in horn is calculated. In this paper, corrugate profiles of horn which satisfy both transition to balanced hybrid condition and fabrication possibility under the mm-wave short wavelength are obtained. Electromagnetic fields inside horn and corrugation are derived by the cylindrical mode theory. Propagation characteristics in the horn are calculated by the mode impedance matching method with boundary conditions, and radiation fields are obtained by the Kirchhoff-Hyugen principle to the horn aperture fields. A mm-wave corrugated horn antenna which operates on $85{\sim}115GHz$ is fabricated by electric forming method. Measurements show that VSWR is under 1.3:1 over whole band and the half power beamwidth on radiation pattern 9.2, 9.16 and 9.02 degree on 85, 100 and 110 GHz are agree well with theoretical calculation.

A Low Power Current-Mode 12-bit ADC using 4-bit ADC in cascade structure (4비트 ADC 반복구조를 이용한 저전력 전류모드 12비트 ADC)

  • Park, So-Youn;Kim, Hyung-Min;Lee, Daniel-Juhun;Kim, Seong-Kweon
    • The Journal of the Korea institute of electronic communication sciences
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    • v.14 no.6
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    • pp.1145-1152
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    • 2019
  • In this paper, a low power current mode 12-bit ADC(: Analog to Digital Converter) is proposed to mix digital circuits and analog circuits with the advantages of low power consumption and high speed operation. The proposed 12 bit ADC is implemented by using 4-bit ADC in a cascade structure, so its power consumption can be reduced, and the chip area can be reduced by using a conversion current mirror circuit. The proposed 12-bit ADC is SK Hynix 350nm process, and post-layout simulation is performed using Cadence MMSIM. It operates at a supply voltage of 3.3V and the area of the proposed circuit is 318㎛ x 514㎛. In addition, the ADC shows the possibility of operating with low power consumption of 3.4mW average power consumption in this paper.

A Vibration Mode Analysis of Cable-type Winding for Distribution Power Transformer by using Transfer Matrix Method (변환행렬법을 이용한 케이블 권선형 배전용 변압기 귄선의 진동모드 해석)

  • Shin, Pan-Seok;Chung, Hyun-Koo;Yoon, Koo-Young
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.23 no.1
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    • pp.85-91
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    • 2009
  • This paper proposes a simulation method of the internal winding fault to calculate the short-circuit current, electromagnetic force and vibration mode in a distribution power transformer by using FEM program(FLUX2D) and analytic algorithm. A usage of the Transfer matrix method is also presented for the vibration mode analysis of the cable-type winding of power transformer. The equations of the winding are approximated by the series expansions of the distributed mass mode and Timoshenko's beam theory. The simulation examples are provided for the cable type winding of the transformer(22.9[kV]/220[V], 1,000[kVA]) to verify the method. The proposed Transfer Matrix Method is also verified by the ANSYS program for the vibration mode of the transformer winding. The method presented may serve as one of the useful tools in the electromagnetic force and vibration analysis of the transformer winding under the short circuit condition.

8.3 Gbps pipelined LEA Crypto-Processor Supporting ECB/CTR Modes of operation (ECB/CTR 운영모드를 지원하는 8.3 Gbps 파이프라인 LEA 암호/복호 프로세서)

  • Sung, Mi-Ji;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.12
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    • pp.2333-2340
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    • 2016
  • A LEA (Lightweight Encryption Algorithm) crypto-processor was designed, which supports three master key lengths of 128/ 192/256-bit, ECB and CTR modes of operation. To achieve high throughput rate, the round transformation block was designed with 128 bits datapath and a pipelined structure of 16 stages. Encryption/decryption is carried out through 12/14/16 pipelined stages according to the master key length, and each pipelined stage performs round transformation twice. The key scheduler block was optimized to share hardware resources that are required for encryption, decryption, and three master key lengths. The round keys generated by key scheduler are stored in 32 round key registers, and are repeatedly used in round transformation until master key is updated. The pipelined LEA processor was verified by FPGA implementation, and the estimated performance is about 8.3 Gbps at the maximum clock frequency of 130 MHz.

Modal Analysis of an Ultrasonic Tool Horn for RFID TAG Micro-pattern Forming (RFID TAG 미세패턴 성형을 위한 공구혼 진동해석)

  • Kim, Kang-Eun;Lee, Bong-Gu;Choi, Sung-Ju
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.12
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    • pp.652-658
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    • 2016
  • In this paper, the theoretical research and simulation using the Finite Element Method (FEM) to design and form a micro-pattern for an ultrasonic horn is described. The present method is based on an initial design estimate obtained by FEM analysis. The natural and resonant frequencies required for the ultrasonic tool horn used for forming the fine pattern were predicted by finite element analysis. FEM analysis using ANSYS S/W was used to predict the resonant frequency for the optimum technical design of the ultrasonic horn vibration mode shape. When electrical power is supplied to the ultrasonic transducer, it is converted into mechanical movement energy, leading to vibration. The RFID TAG becomes the pattern formed on the insulating sheet by using the longitudinal vibration energy of the ultrasonic tool horn. The FEM analysis result is then incorporated into the optimal design and manufacturing of the ultrasonic tool horn.