• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.521-531
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• 2009

Flash memory has physical characteristics different from hard disk where two costs of a read and write operations differ each other and an overwrite on flash memory is impossible to be done. In order to solve these restrictions with software, storage systems equipped with flash memory deploy FTL(Flash Translation Layer) software. Several FTL algorithms have been suggested so far and most of them prefer sequential write pattern to random write pattern. In this paper, we provide a new technique to efficiently store and maintain the B-tree index on flash memory. The operations like inserts, deletes, updates of keys for the B-tree generate random writes rather than sequential writes on flash memory, leading to inefficiency to the B-tree maintenance. In our technique, we convert random writes generated by the B-tree into sequential writes and then store them to the write-buffer on flash memory. If the buffer is full later, some sequential writes in the buffer will be issued to FTL. Our diverse experimental results show that our technique outperforms the existing ones with respect to the I/O cost of flash memory.

• Journal of the Korea Computer Industry Society
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• v.6 no.2
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• pp.295-304
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• 2005

This paper presents the problem of exhaustive test generation for detection of coupling faults between cells in word-oriented memories. According to this fault model, contents of any w-bit memory word in a memory with n words, or ability tochange this contents, is influenced by the contents of any other s-1 words in the memory. A near optimal iterative method for construction of test patterns is proposed The systematic structure of the proposed test results in simple BIST implementations.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.122-127
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• 2012

A nano-electro-mechanical (NEM) memory simulator has been developed by using Matlab. The simulator can be used for the prediction of hysterisis curves, applied forces, steady- or transient-state behavior, program/erase energy consumption and potential energy. Predicting NEM memory behavior by simple user interface, the simulator will make the design of NEM memory cells simpler.

• Science of Emotion and Sensibility
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• v.14 no.1
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• pp.117-126
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• 2011

This study investigates the physical properties and manufacturing method of shape memory fabric for emotional garment made by polypropylene. For this purpose, polypropylene(PP) POY and SDY were texturized using low temperature and constant length heat treatment texturing technologies, respectively. The shape memory fabrics made using these texturized PP yarns were woven with two kinds of PET and PTT shape memory yarns on the air-jet loom and the various physical properties of four kinds of shape memory fabrics were measured and discussed. The tenacity and breaking strain of PP texturized yarns treated by low temperature and constant length heat treatment showed high weaving efficiency and the wet thermal shrinkage of PP textured yarns was shown less than 1.5%, dry thermal shrinkage was ranged between 3% and 5%, which means thermal stability compared to the PTT textured yarn with high thermal shrinkage, 5~8%. The shape memory characteristics of PP shape memory fabrics measured by Toray method showed five grade as same value as PTT shape memory fabric. The heat keeping property of the PP shape memory fabric showed 56% higher value than that of PTT shape memory fabric. The water repellency of PP shape memory fabric measured by spray method showed five grade as same value as PTT shape memory fabric treated with water repellent agent. Especially, shape memory properties of PP shape memory fabric measured by 3-D image and camera measurement methods showed similar characteristics to the PTT shape memory fabric.

• The KIPS Transactions:PartA
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• v.15A no.5
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• pp.269-274
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• 2008

Recently, lots of embedded processors which can run streaming multimedia with high resolution display are introduced. Among the applications running on these embedded processors, real-time audio streaming is one of the applications that suffer from the lack of energy and memory space. In this paper, we propose a novel data compression method on scratch-pad memory, which saves both useful space on the scratch-pad memory and energy. We have implemented the data compression scheme on the GDM1202 real-time audio streaming processor, and the performance results show that we obtained 13.3% energy saving while maintaining comparable application performance to that of the non-compression case.

• KIISE Transactions on Computing Practices
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• v.23 no.3
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• pp.165-170
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• 2017

Many studies have utilized GPGPU (General-Purpose Graphic Processing Unit) and its high computing power to compute complex tasks. The characteristics of GPGPU programs necessitate the operations of memory copy between the host and device. A high latency period can affect the performance of the program. Thus, it is required to significantly improve the performance of GPGPU programs by optimizations. By executing multiple GPGPU programs simultaneously, the latency hiding effect of memory copy is achieved by overlapping the memory copy and computing operations in GPGPU. This paper presents the results of analyzing the latency hiding effect for memory copy operations. Furthermore, we propose a performance anticipation model and an algorithm for the limitations of using pinned memory, and show that the use of the proposed algorithm results in a 41% performance increase.

• Journal of Internet Computing and Services
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• v.11 no.4
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• pp.95-106
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• 2010

Recently multiple process communicate together. They share resource and information for cooperation in complicated programming environment. Kernel provides IPC (Inter -Process Communication) for communication with each other process. Shared Memory is a technique that many processes can access to identical memory area in the Linux environment. In this paper, we propose a performance improvement method of shared memory in the dual-core embedded linux system which is consist of different core and different operating system. We construct the MPC2530F (ARM926F+ARM946E) linux system and measure the performance therein. We attempt a performance enhancement in each CPU for each process which uses a shared memory.

• The Transactions of the Korea Information Processing Society
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• v.5 no.1
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• pp.24-32
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• 1998

The bus contention among bus-based shared-memory multiprocessors limits their performance. In addition, under split bus transaction environment, multiprocessors may make some memory requests unnecessary stand by in the memory access buffer, which makes system performance worse. This unnecessary stand-by can be eliminated by maintaining the bitmap table which contains the status bit for each memory block. However, this mechanism requires a great size of SRAM for the status information, which is fully mapped from the whole memory blocks. To solve this problem, we propose a bitmap cache which exploits partial mapping and locality of references. The simulation results show that the proposed system can greatly reduce the capacity of SRAM for the status information with little deteriorating its performance.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.6
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• pp.19-28
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• 2005

The multiprocessor architecture is a good method to improve the computer system performance. The CC-NUMA provides a single shared space with the physically distributed memories is used widely in the multiprocessor computer system. A CC-NUMA has the full-mapped directory for the shared memory md uses a remote cache memory for tile fast memory access. In this paper, we propose a processing node architecture for a CC-NUMA system and a cache coherency protocol on the physically distributed but logically shared system. We show an implementation result of the system which is adopted the cache coherency protocol.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.2
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• pp.275-282
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• 2015

Since a NAND-flash memory is able to keep data during electricity-off and has small cost to store data per bytes, it is widely used on hand-held devices. It is necessary to use an index in order to process mass data effectively on the flash memory. However, since the flash memory requires high cost for a write operation and does not support an overwrite operation, it is possible to reduce the performance of the index when the disk based index is exploited. In this paper, we implement the fixed grid file index and evaluate the performance of the index on various conditions. To do this, we measure the average processing time by the ratio of query operations and update operations. We also the compare the processing times of the flash memory with those of the magnetic disk.