• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.6
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• pp.787-798
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• 1995

We implement the E-plane T-juncition manifold mutiplexer having low insertion loss for output multiplexer of Ku-band satellite transponder. Manifold multiplexer implemented here is composed of 2 channel filters, T-junctions, half-wave waveguide connecting channel filters and manifold, and manifold itself.[1-4] Considering the mass and volume of the satellite transponder, the channel filters are designed to dual-mode.[5-13] And Elliptic filter function is used, which has good characteristics of suppressing the interference between 2 channels. Since the performance of manifold multiplexer depends on the manifold waveguide transmission line length, it's necessary proper analysis. In this paper, we do optimization process of T-junction and other elements by using CAD and implement the manifold multiplexer. An experiment shows that characteristic response of multiplexer matches wel its modeling result.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.675-676
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• 2013

This paper presents a design method for multiple-output combinational digital logic systems using time domain based on multiplexing and common multi-terminal extension decision diagrams. The common multi-terminal extension decision diagrams represents extension valued multiple-output functions, while time domain based on multiplexing systems transmit several signals on a single lines. The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams, that is the common binary decision diagrams and common multi-terminal extension decision diagrams.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.117-124
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• 1993

In this paper we propose a new thchnology mapping algorithm for multiplexer-based FPGA's The algorithm consists of three phases` First, it converts the logic functions and the basic logic mocule into BDD's. Second. it covers the logic function with the basic logic modules. Lastly, it reduces the number of basic logic modules used to implement the logic function after going through cell merging procedure. The binate selection is employed to determine the order of input variables of the logic function to constructs the balanced BDD with low level. That enables us to constructs the circuit that has small size and delay time. Technology mapping algorithm of previous work used one basic logic module to implement a two-input or three-input function in logic functions. The algorithm proposed here merges almost all pairs of two-input and three-input functions that occupy one basic logic module. and improves the mapping results. We show the effectiveness of the algorithm by comparing the results of our experiments with those of previous systems.

• Journal of Korean Institute of Industrial Engineers
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• v.22 no.3
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• pp.387-398
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• 1996

In this study the cell arrival processes from pre-buffer into multiplexer for MPEG(Motion Picture Experts Group) coding video sources are analyzed with consideration of the traffic periodicity in frame level. The analysis is performed by introducing the two arrival models, that is, periodic on/off source model and periodic uniform arrival model. Modulated $N^*D$/D/1 queueing system is utilized in periodic on/off source model, while ${\Sigma}{N_i}^*D_i$/D/1 queueing system is used in periodic uniform arrival model. The presented models are validated by comparing with computer simulations. Numerical results for periodic uniform arrival model are shown to be very accurate, but those of periodic on/off source model are shown to be inaccurate as the number of sources are increased.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.3
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• pp.119-123
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• 2006

The orthogonal frequency-division multiplexing (OFDM) technique is well known to be robust against the frequency-selective fading in wireless channels. It is due to the exploitation of a guard interval that is inserted at beginning of each OFDM symbol. Based on the conventional OFDM and a polyphase filtered orthogonal frequency division multiplexing (PF-OFDM) technique, we developed an adaptive beamforming algorithm for antenna arrays. The proposed algorithm would lead to an efficient use of channel, since it is possible to eliminate a guard interval and also easily suppress interchannel interference at the same time. In this paper, a series of computer simulations have been provided to show the performance of the proposed system.

• Journal of IKEEE
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• v.19 no.2
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• pp.271-275
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• 2015

This paper proposes a unified HEVC $4{\times}4$ IDCT/IDST architecture for area reduction. In general, $4{\times}4$ IDCT and $4{\times}4$ IDST blocks are implemented separately, and they are connected with multiplexers. In the proposed arechitecture, these two blocks are unified, and internal hardware resources such as multipliers are shared. This reduces the chip area. The synthesized block in 0.18 um technology is 2,795 gates, and the gate count is reduced by 9.44% in comparison with conventional designs.

• Journal of IKEEE
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• v.14 no.4
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• pp.283-290
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• 2010

This study is on the design of 10Gbps CMOS receiver circuits for fiber-optic communication. The receiver is made up of a photodiode, a transimpedance amplifier, a limiting amplifier, an equalizer, a clock and data recovery loop circuit, and a demultiplexer or demux with some auxiliary circuits including I/O circuits. Various wideband or high-speed circuit techniques are harnessed to realize a feasible, effective, and reliable receiver for a SONET fiber-optic standard, OC-192.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.288-291
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• 2003

본 논문에서는 모듈성과 확장성을 갖는 시스톨릭 어레이를 이용한 두 띠 행렬의 비트 연속 승산기 구현에 대하여 기술한다. 띠 폭이 3인 4$\times$4 띠 행렬이 주어질 때 워드 레블 승산기 설계를 위한 3차원 DG로부터 2차원 시스톨릭 어레이를 유도한 후, 워드 레블 PE를 비트 연속 승산기와 가산기를 이용하여 비트 레블 PE로 변환시켜 띠 행렬의 비트 레블 승산기를 설계한다. 구현된 워드 레블 승산기와 비트 레블 승산기는 RT 수준에서 VHDL로 모델링하여 동작을 검증하였다. 검증된 시스톨릭 어레이를 이용한 워드 레블 승산기와 비트 레블 승산기는 Hynix에서 제공하는 0.35$\mu\textrm{m}$ 셀 라이브러리를 사용하여 Synopsys design compiler로 합성되었다.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04b
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• pp.517-519
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• 2004

MPEG-4는 이미지, 비디오. 오디오와 다양한 기하객체 및 텍스트객체 등 설러 가지 멀티미디어 데이터를 각 객체 단위로 합성하여 멀티미디어 컨텐츠를 구성함으로써 멀티미디어 데이터에 대한 재사용성과 효율성을 높이며, 사용자와의 상호작용이 가능한 시청각 장면을 생성하고 전송을 가능하게 한다. 유비쿼터스 컴퓨팅에 대한 연구가 개발하게 전개되고 있는 이때, PC에서뿐만 아니라 언제 어디서나 가능한 모바일 환경에서 다양한 사용자 인터랙션에 중점을 두고 카드메일, 간단 게임 저작 등을 가능하게 함으로써 poA환경에서 전문적인 저작도구를 개발하는 것이 필요하다. 본 논문은 poA환경에서 기하객체와 텍스트, 이미지 등의 객체들을 이용하여 MPEG-4 컨텐츠 저작을 위한 씬 트리를 생성하고 이에 대한 인코딩을 통하여 BIFS 파일 포맷을 형성하고 멀티플렉서를 통하여 MPEG-4 파일을 생성함으로써 PDA환경에서 직접적이고도 시각적인 저작이 가능한 MPEG-4 건텐츠 저작시스템을 제안하고 그 개발 결과를 보인다.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.04a
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• pp.231-234
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• 2001

본 논문은 다단계 상호연결망에서 높은 처리율과 결함 허용을 위해 중복 경로를 제공하는 E-Cube-network 구조를 제안한다. Cube network의 확장된 형태인 E(Extended)-Cube network 구조를 통해 패킷 전송중 충돌이 발생한 경우 스위치 자신을 순환하고, 재차 충돌이 발생하면 멀티플렉서를 통해 또 다른 새로운 경로로 패킷을 전송하는 새로운 알고리즘을 제시한다. 그리고 모의실험을 통해 기존의 Cube network 구조보다 높은 종단간 처리율을 보인다.