Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Design of Unified HEVC 4×4 IDCT/IDST Block

HEVC 4×4 IDCT/IDST 통합 블록 설계

  • Jung, Seulkee (School of Electronic Engineering, Soongsil University) ;
  • Lee, Seongsoo (School of Electronic Engineering, Soongsil University)
  • Received : 2015.06.15
  • Accepted : 2015.06.26
  • Published : 2015.06.30
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Abstract

This paper proposes a unified HEVC $4{\times}4$ IDCT/IDST architecture for area reduction. In general, $4{\times}4$ IDCT and $4{\times}4$ IDST blocks are implemented separately, and they are connected with multiplexers. In the proposed arechitecture, these two blocks are unified, and internal hardware resources such as multipliers are shared. This reduces the chip area. The synthesized block in 0.18 um technology is 2,795 gates, and the gate count is reduced by 9.44% in comparison with conventional designs.

본 논문은 HEVC $4{\times}4$ IDCT/IDST를 위한 통합형 아키텍쳐를 제안하여 면적을 줄이고자 한다. $4{\times}4$ IDCT와 $4{\times}4$ IDST는 일반적으로 따로따로 만들어서 멀티플렉서로 연결하여 사용하나, 제안하는 아키텍쳐 구현에서는 두 블록을 합쳐서 곱셈기 등의 하드웨어 자원을 공유하여 면적을 줄였다. 0.18um 공정에서 합성한 결과 게이트 수가 약 2,795 게이트로 기존 아키텍쳐 대비 9.44% 감소함을 확인하였다.

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References

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