• The Journal of the Korea institute of electronic communication sciences
• /
• v.16 no.4
• /
• pp.591-598
• /
• 2021

The digital phase-locked loops(DPLL) is a circuit used for phase synchronization and has been generally used in various fields such as communication and circuit fields. State estimators are used to design digital phase-locked loops, and infinite impulse response state estimators such as the well-known Kalman filter have been used. In general, the performance of the infinite impulse response state estimator-based digital phase-locked loop is excellent, but a sudden performance degradation may occur in unexpected situations such as inaccuracy of initial value, model error, and disturbance. In this paper, we propose a minimum variance finite impulse response filter with optimal horizon for designing a new digital phase-locked loop. A numerical method is introduced to obtain the measured value interval length, which is an important parameter of the proposed finite impulse response filter, and to obtain a gain, the covariance matrix of the error is set as a cost function, and a linear matrix inequality is used to minimize it. In order to verify the superiority and robustness of the proposed digital phase-locked loop, a simulation was performed for comparison and analysis with the existing method in a situation where noise information was inaccurate.

• Journal of Astronomy and Space Sciences
• /
• v.14 no.2
• /
• pp.386-394
• /
• 1997

In this study, a few of the modeling methods for flexible spacecraft were introduced and adopted to the modeling of a 3-axes stabilization satellite. The generated model was put into pre-built rigid body attitude control loop. A Lumped Parameter Model(Global Mode Model: GMM) was recommended for the absence of the Finite Element Method(FEM) model. Finally, GMM was compared with FEM in terms of designing a control filter. A 1st-order filter was designed to meet requirements of the controller since the new flexible model was applied, and that filter was added to motor controller and axis controller. MATLAB/Simulink was used as a tool for design and simulation of the control loop and filter.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.6
• /
• pp.51-56
• /
• 2010

In this paper, a novel Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF. The size of chip is $255{\mu}m$ $\times$ $935.5{\mu}m$ including the LF. The proposed P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.48 no.5
• /
• pp.46-54
• /
• 2011

In this paper, we propose a low-complexity loop filtering method depending on transform-block regions. Block adaptive loop filter (BALF) was developed to improve about 10% in compression performance for the next generation video coding. The BALF employs the Wiener filter that makes reconstructed frames close to the original ones and transmits filter-related information. However, the BALF requires high computational complexity, while it can achieve high compression performance because the block adaptive loop filter is applied to all the pixels in blocks. The proposed method is a new loop filter that classifies pixels in a block into inner and boundary regions based on the characteristics of the integer transform and derives optimum filters for each region. Then, it applies the selected filters for the inner and/or boundary regions. The decoder complexity can be adjusted by selecting region-dependent filter to be used in the decoder side. We found that the proposed algorithm can reduce 35.5% of computational complexity with 2.56% of compression loss, in case that only boundary filter is used.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.19 no.1
• /
• pp.31-38
• /
• 2024

The digital phase-locked loop(DPLL) is one of the circuits composed of a digital detector, digital loop filter, voltage-controlled oscillator, and divider as a fundamental circuit, widely used in many fields such as electrical and circuit fields. A state estimator using various mathematical algorithms is used to improve the performance of a digital phase-locked loop. Traditional state estimators have utilized Kalman filters of infinite impulse response state estimators, and digital phase-locked loops based on infinite impulse response state estimators can cause rapid performance degradation in unexpected situations such as inaccuracies in initial values, model errors, and various disturbances. In this paper, we propose a two-layer Frobenius norm-based finite impulse state estimator to design a new digital phase-locked loop. The proposed state estimator uses the estimated state of the first layer to estimate the state of the first layer with the accumulated measurement value. To verify the robust performance of the new finite impulse response state estimator-based digital phase locked-loop, simulations were performed by comparing it with the infinite impulse response state estimator in situations where noise covariance information was inaccurate.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
• /
• 1995.10a
• /
• pp.241-248
• /
• 1995

본 연구에서 얻어진 주된 결과를 요약하면 다음과 같다. 1) 모달필터의 오차로 인해 모달상태 추정에 오차가 발생할 때, 폐루프 진동제어계가 Lyapunov 점근 안정성을 갖기 위한 필요충분 조건식(26)을 유도하였다. 2) 모달필터의 오차가 클수록 폐루프 진동제어계의 안정성은 점점 나빠지게 된다. 3) 모달필터의 오차 .DELTA.D가 존재할 때, L$_{\infty}$-놈 이론을 적용하여 진동제어 응답성능의 오차의 상한, 식(32)를 유도하였다. 4) 응답성능 오차의 상한은 모달필터 오차 .DELTA.D의 크기에 비례하고 있으며, 비례계수는 모달공간에서의 제어기법이 종류에 따라 다르다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.11 no.3
• /
• pp.283-289
• /
• 2018

A PLL with an unipolar charge pump and a loop filter consisting of sample-hold capacitor and Fvco-sampled feedforward loop filter. The proposed PLL not only reduces the chip area by replacing the resistance to a switch and a small capacitor but also reduces the variation of ${\Delta}VLPF$ and ${\Delta}{\Delta}VLPF$ to 1/6 and 1/5 respectively. The variation of ${\Delta}VLPF$ is related to the phase noise of VCO output and that of ${\Delta}{\Delta}VLPF$ is proportional to reference spurs. It has been simulated and verified with a 1.8V $0.18{\mu}m$ CMOS process and shown a good phase noise characteristics. We plan to fabricate chip based on the simulations and check performance.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.5
• /
• pp.1103-1108
• /
• 2010

In this paper, Frequency Synthesizer which is widely used for FH-SS system is proposed and the experimental results are analyzed. The performance of the DPLL(Digital Phase-Locked-Loop), which is the main part of the Synthesizer is analyzed by the computer program. Using Maxplus-II tool provided by altera. co., ltd, each part of the DPLL is designed and all of them is integrated into EPM7064SLC44-10 chip. And the simulation results are compared with the characteristics of the implemented circuits for analysis. And the experiential results show that the N value of the loop filter is toggled to adjacent N value, which result in phase jitter of the output. It can be resolved by increasing DCO(Digital Controlled oscillator) clock rate.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.11 no.5
• /
• pp.531-537
• /
• 2018

A novel PLL with a delta-sigma modulator and a spur reduction circuit is proposed. delta-sigma modulator makes the LF remove noise easily by moving the spur noise to a higher frequency band. Therefore, the magnitude of spur can be reduced the reasonable bandwidth. The spur reduction circuit reduces the spur size by reducing the LF voltage change generated during the period of reference signal. The spur reduction circuit is designed as simple as possible not to increase the size of PLL. The proposed PLL with the previous two techniques is designed with a supply voltage of 1.8V in a 0.18um CMOS process. Simulation results show an almost 20dB reduction in the magnitude of spur. The spur reduced PLL can be used in narrow bandwidth communication system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.11 no.6
• /
• pp.651-657
• /
• 2018

A novel PLL with a delta-sigma modulator and a spur reduction circuit is proposed. delta-sigma modulator makes the LF remove noise easily by moving the spur noise to a higher frequency band. Therefore, the magnitude of spur can be reduced the reasonable bandwidth. The spur reduction circuit reduces the spur size by reducing the LF voltage change generated during the period of reference signal. The spur reduction circuit is designed as simple as possible not to increase the size of PLL. The proposed PLL with the previous two techniques is designed with a supply voltage of 1.8V in a 0.18um CMOS process. Simulation results show an almost 20dB reduction in the magnitude of spur. The spur reduced PLL can be used in narrow bandwidth communication system.