• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.12 s.115
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• pp.1231-1239
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• 2006

In this research magnetic field reduction effect of each passive loop was analyzed by using the scale down models of transmission lines. This paper examined magnetic field reduction effect of the passive loop that will be applied to actual facility through the experiment, which is about double vertical transmission line and horizontal transmission line. Consequently, by confirming the fact that magnetic field reduction effect can be obtained to 50 % by passive loop without reactive compensation, we insured technology about application of passive loop. And the case of 3 turns of loop showed two times reduction effect than that of 1 turns of loop in reducing magnetic field. Vertical passive loop is more efficient than horizontal passive loop in the aspect of reducing magnetic field on double vertical transmission lines. What is more, vertical passive loop showed good effect of reducing magnetic field in a far distance as well as in a short distance.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.5
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• pp.531-537
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• 2018

A novel PLL with a delta-sigma modulator and a spur reduction circuit is proposed. delta-sigma modulator makes the LF remove noise easily by moving the spur noise to a higher frequency band. Therefore, the magnitude of spur can be reduced the reasonable bandwidth. The spur reduction circuit reduces the spur size by reducing the LF voltage change generated during the period of reference signal. The spur reduction circuit is designed as simple as possible not to increase the size of PLL. The proposed PLL with the previous two techniques is designed with a supply voltage of 1.8V in a 0.18um CMOS process. Simulation results show an almost 20dB reduction in the magnitude of spur. The spur reduced PLL can be used in narrow bandwidth communication system.

• The KIPS Transactions:PartD
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• v.15D no.2
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• pp.197-206
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• 2008

The CTOC framework was implemented to efficiently perform analysis and optimization of the Java bytecode that is often being used lately. In order to analyze and optimize the bytecode from the CTOC, the eCFG was first generated. Due to the bytecode characteristics of difficult analysis, the existing bytecode was expanded to be suitable for control flow analysis, and the control flow graph was drawn. We called eCFG(extended Control Flow Graph). Furthermore, the eCFG was converted into the SSA Form for a static analysis. Many loops were found in the conversion program. The previous CTOC performed conversion directly into the SSA Form without processing the loops. However, processing the loops prior to the SSA Form conversion allows more efficient generation of the SSA Form. This paper examines the process of finding the loops prior to converting the eCFG into the SSA Form in order to efficiently process the loops, and exhibits the procedures for generating the loop tree.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.651-657
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• 2018

A novel PLL with a delta-sigma modulator and a spur reduction circuit is proposed. delta-sigma modulator makes the LF remove noise easily by moving the spur noise to a higher frequency band. Therefore, the magnitude of spur can be reduced the reasonable bandwidth. The spur reduction circuit reduces the spur size by reducing the LF voltage change generated during the period of reference signal. The spur reduction circuit is designed as simple as possible not to increase the size of PLL. The proposed PLL with the previous two techniques is designed with a supply voltage of 1.8V in a 0.18um CMOS process. Simulation results show an almost 20dB reduction in the magnitude of spur. The spur reduced PLL can be used in narrow bandwidth communication system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2C
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• pp.191-200
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• 2002

A frequency synthesizer that can be used in IMT-2000 was designed and fabricated using dual loop PLL(Phase Locked Loop) in this paper. For improving phase noise characteristic two loops, reference loop and main loop, were divided. Phase noise was improved by transformed clamp type voltage controled oscillator and optimizing loop bandwidth in reference loop. And voltage controlled oscillator open loop gain in main loop. Fabricated the frequency synthesizer had 1.81GHz center frequency, 160MHz tuning range, 13.5dBm output power and -119.73dBc/Hz low phase noise characteristic.

• Journal of KIISE:Software and Applications
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• v.33 no.5
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• pp.489-498
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• 2006

In this paper, we suggested a vehicle classification algorithm using pattern recognition method. At present, Inductive Loop Detector is rarely used for vehicle classification because of its low accuracy. To improve the accuracy, we suggest a new algorithm for Loop Detector using neural networks. In the developed algorithm, the inputs to the neural networks are the variation rate of frequency and occupancy-time. The output is classified vehicles. The developed algorithm was assessed at test sites and the recognition rate was 91.3percent. The results verified that the proposed algorithm improves the vehicle classification accuracy compared to the conventional method based on Loop Detector.

• Economic and Environmental Geology
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• v.20 no.1
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• pp.77-82
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• 1987

An analysis is made for the relative effectiveness in detecting a subsurface thin layer by four electromagnetic depth sounding systems; horizontal coplanar loops, perpendicular loops, vertical coplanar loops and vertical coaxial loops. The moduli and phases of mutual coupling ratios over a three-layered earth for the four systems are evaluated rapidly by the related convolution technique. Root mean square differences between the responses from the three-layered and the homogeneous earths are used to compare the relative effectiveness of the systems quantitatively. Comparing the all systems, it is found that the perpendicular loop system appears to be the most superior to the other systems.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.2
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• pp.186-196
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• 2000

In this paper, modified square loop frequency selective surface for dualband communication antenna systems is proposed, and the scattering characteristics is discussed. The analysis for the problem of scattering by periodic structures with a dielectric slab is formulated using the spectral-domain immittance approach and Floquet's theorem. The method of moments which uses rooftop subdomain basis function is employed to solve the equations. Numerical results include the comparison between the transmission characteristic of general square loop and that of modified square loop. Also, the transmission characteristics of modified square loop for arbitrary incident angle and polarization is presented. To verify analysis results, modified square loop frequency selective surface was fabricated and the calculated results were compared with the measured results. The measured results showed good agreement with the calculated results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.7
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• pp.649-656
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• 2002

This paper addresses the phase noise analysis of high-speed DH-PLL(Digital Hybrid Phase-Locked Loops) frequency synthesizer. Because of the additional quantization noise of D/A converter in DH-PLL, the phase noise of DH-PLL is increased than the conventional PLL. Three kinds of noise sources such as reference input, D/A converter, and VCO(Voltage Controlled Oscillator) are considered to analyze the phase noise. It largely depends on the closed loop bandwidth and frequency synthesis division ratio(N) so that we can decide the optimal closed loop bandwidth to minimize the phase noise of DH-PLL. It is shown that the simulation results closely match with the results of analytical approach.

• Proceedings of the KIEE Conference
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• 2003.07a
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• pp.564-566
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• 2003

전력 계통에서 안정한 전력을 공급하는 것은 매우 중요하다. 전력 계통의 오류는 전압 및 주파수를 감시함으로써 검출 가능하다. 본 논문에서는 디지털 위상 고정 루프를 이용한 전력 계통의 주파수 측정 장치를 제안하고 이를 구현한 결과를 제시하고자 한다. 제안한 주파수 측정 장치는 위상 고정 루프의 기본요소로 구성된다. 위상분별기는 배타적 논리연산을 통해 위상오차를 검출하고 위상의 앞섬 및 뒤짐의 검출이 가능하도록 설계하였으며, 전력 계통의 주파수 동특성을 고려해서 3차의 루프 필터를 설계하였다. DCO는 출력 주파수의 분해능을 고려하여 입력 신호를 정확하게 추정할 수 있도록 설계하였다. 제안한 주파수 측정 장치의 성능을 검증하기 위하여 모의실험을 통해 주파수 변동량의 측정 범위 및 정확도를 검토하였으며, FPGA와 CPU를 포함하는 하드웨어를 구현하였다. FPGA에는 Verilog HDL로 디지털 위상 고정 루프의 위상분별기와 DCO를 구현하였으며 루프필터는 소프트웨어로 구현하였다. 제안한 디지털 위상 고정 루프의 성능 검증을 위해 정밀한 함수 발생기의 출력을 인가한 후 출력 주파수를 측정한 결과 및 전력 계통에 대한 실험 결과를 제시하였다.