• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.357-358
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• 2014

본 논문에서는 태양광 모듈의 최대 전력점을 추종하기 위한 제어 기법으로 부스트 컨버터(boost converter)의 불연속 전류모드(Discontinuous Current Mode)에서 주파수를 제어하는 기법을 구현 하였다. 태양광 모듈에 연결된 부스트 컨버터는 전압루프를 통하여 Perturb and Observation(P&O)기법을 사용하여 최대 전력점을 추종하였다. 부스트 컨버터의 인덕터에 흐르는 전류는 불연속 전류모드로 제어 된다. 불연속 전류모드에서의 제어기 설계는 MATLAB과 PSIM의 전달함수특성을 수학적 모델링을 통하여 비교 검증 하였으며, 모든제어는 MCU(TEXAS INSTRUMENTS사의 DSPF28335)를 통해 디지털로 제어 하였다. 제안된 기법은 단일 PV모듈이 연결된 불연속전류모드 부스트 컨버터를 통해 동작특성을 분석하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.543-545
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• 2017

This paper describes the SAO hardware architecture design for high performance in-loop filters. SAO is an inner module of in-loop filter, which compensates for information loss caused by block-based image compression and quantization. However, HEVC's SAO requires a high computation time because it performs pixel-unit operations. Therefore, the SAO hardware architecture proposed in this paper is based on a $4{\times}4$ block operation and a 2-stage pipeline structure for high-speed operation. The information generation and offset computation structure for SAO computation is designed in a parallel structure to minimize computation time. The proposed hardware architecture was designed with Verilog HDL and synthesized with TSMC chip process 130nm and 65nm cell library. The proposed hardware design achieved a maximum frequency of 476MHz yielding 163k gates and 312.5MHz yielding 193.6k gates on the 130nm and 65nm processes respectively.

• 전기의세계
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• v.45 no.1
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• pp.28-32
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• 1996

드라이브 기술의 최신동향 및 향후 전망에 대해 앞으로 전개될 항목을 간략히 요약하면 다음과 같다. 1. 모듈화 및 소형화 2. 직류 전압원의 고전압화 3. 드라이브와 NC간의 간편한 연결 4. NC의 조작화면을 통한 손쉬운 파라미터 조정 5. 디지탈 폐루프 제어 채용(FULL 디지탈화) 6. 에너지 절감형 모델 개발 7. 사용자 편의 기능의 확대 서보/스핀들 드라이브 설계기술의 최신동향 및 향후 개발 전망에 대해서 특징, 기능을 중심으로 이상과 같이 간략하게 설명하였다. 본고가 드라이브 기술 개발에 힘쓰는 관련 engineer들에게 조금이나마 참고가 되길 기대한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.25-33
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• 2007

In this paper, a fourth-order single-bit delta-sigma modulator is presented and implemented. The loop-filter is composed of both feedback and feedforward paths. Measurement results show that maximum 99dB dynamic range is achievable at a clock rate of 3.2MHz for 20kHz baseband. The proposed modulator has been fabricated in a $0.18{\mu}m$ standard CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.11-17
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• 2004

This paper describes the implementation of monolithic optical transceiver circuitry being used as a part of the fiber optic modules. It has been fabricated in 0.6 ${\mu}{\textrm}{m}$ 2-poly 3-metal silicon CMOS analog technology and operates at 155.52 Mbps(STM-1) data rates. It drives laser diode to transmit intensity modulated optical signal according to 155.52 Mbps electrical data from system. Also, it receives 155.52 Mbps optical data that transmitted from other systems and converts it to electrical data using photo diode and amplifier. To avoid noise and interference between transmitter and receiver on one chip, layout techniques such as special placement, power supply separation, guard ring, and protection wall were used in the design. The die area is 4 ${\times}$ 4 $\textrm{mm}^2$, and it has 32.3 ps rms and 335.9 ps peak to peak jitter on loopback testing. the measured power dissipation of whole chip is 1.15 W(230 mW) with a single 5 V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.171-177
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• 2006

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver with the clock-hold function has been designed and implemented. It consists of a clock extractor circuit, an RF mixer and a frequency discriminator for phase/frequency detection, a VC-DRO, a phase shifter, and a clock-hold circuit. The extracted 40 GHz clock is synchronized with a stable 10 GHz VC-DRO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module are significantly improved as compared with those of the conventional open-loop type clock recovery module with a DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When an input signal is dropped, the 40 GHz clock is maintained continuously by the hold circuit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.36 no.11
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• pp.1335-1343
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• 2012

In this study, the lightweight modular design of hybrid railway carbody structures made of sandwich composites and aluminum extrusions was investigated by using topology and size optimization techniques. The topology optimum design was used to select the best material for parts of the carbody structure at the initial design stage, and then, the size optimum design was used to find the optimal design parameters of hybrid carbody structures using first-order and sub-problem methods. Through the topology optimization analysis, it was found that aluminum extrusions were suitable for primary members such as the underframe and lower side panel module to improve the stiffness and manufacturability of the carbody structures, and sandwich composites were appropriate for secondary members such as the roof and middle side panel module to minimize its weight. Furthermore, the results obtained by size optimization analysis showed that the weight of hybrid carbody structures composed of aluminum extrusions and sandwich composites could be reduced by a maximum of approximately 17.7% in comparison with carbody structures made of only sandwich composites.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.51-59
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• 2009

This paper presents the design of continuous-time sigma-delta modulator for acoustic sensor. The feedforward structure without summing block is used to reduce power consumption of sigma-delta modulator. A high-linearity active-RC filter is used to improve resolution of sigma-delta modulator. Excess loop delay problem in conventional continuous-time sigma-delta modulators is solved by our proposed architecture. A low power, high resolution fourth-order continuous-time sigma-delta modulator with 1-bit quantization was realized in a 0.13-${\mu}m$ 1-Poly 8-metal CMOS technology, with a core area of $0.58\;mm^2$. Simulation results show that the modulator achieves 91.3-dB SNR over a 25-kHz signal bandwidth with an oversampling ratio of 64, while dissipating $290{\mu}W$ from a 3.3-V supply.

• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.1
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• pp.88-93
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• 2010

In this paper, an edge detecting sensor using ultrasonic detection module is developed which will be used for areas of industrial applications such as plastic film winding system, cloth winding system, paper roll industry, etc. The developed sensor have properties that more exactly detect the edge line, that less affected by environmental noise, and that it produced more stable measurement output. The mass of the winding object is dominantly affect the dynamics of the system and it could produce undesirable result of the system such as stability of the closed-loop system and accuracy of edge-line-following-control(ELFC) objective. Also, there exist sensor noise due to the mechanical vibration or other environmental effect. These noise also degrade the efficiency of control system. In order to compensate these problems, this paper present a fuzzy PI/PID edge-line-controller, and which is designed and implemented.