• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.322-324
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• 2004

보안 시스템은 암호화 기능을 필요로 하고 암호화를 위 한 비밀키로 난수를 사용한다 난수 발생기에는 순수 난수 발생기와 의사 난수 발생기가 있다. 본 논문에서는 펜티엄부터 인텔 프로세서들이 가지고 있는 타임스탬프 카운터 레지스터(TSC MSR)에서 시드를 가져와 비트 가공을 통해 난수를 발생하는 난수 발생기를 구현하였다. 구현된 난수 발생기의 난수 품질을 평가하기 위해 순수 난수 발생기, 의사 난수 발생기의 난수 시퀀스와 비교하였다. 구현된 난수 발생기가 생성한 난수 시퀀스는 순수 난수 발생기의 난수 시퀀스와 큰 차이가 없고 특정 디바이스 없이 응용이 간단하다는 점에서 보안 시스템의 암호화키로 사용하기에 적합하다.

• The Magazine of the IEIE
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• v.11 no.5
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• pp.75-87
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• 1984

• The KIPS Transactions:PartA
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• v.18A no.6
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• pp.265-270
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• 2011

Even though 32-bit ISA based microprocessors are widely used more and more, 16-bit ISA based processors are still being frequently employed for embedded systems. Intel 8086, 80286, Motorola 68000, and ADChips AE32000 are the representatives of the 16-bit ISA based processors. However, due to less expressiveness of the 16-bit ISA from its narrow bit width, we need to execute more 16-bit instructions for the same implementation compared to 32-bit instructions. Because the number of executed instructions is a very important factor in performance, we have to resolve the problem by improving the expressiveness of the 16-bit ISA. In this paper, we propose a new pair register allocation algorithm to enhance an original graph-coloring based register allocation algorithm. Also, we explain about both the performance result and further research directions.

• The KIPS Transactions:PartC
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• v.11C no.3
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• pp.387-394
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• 2004

One of the main challenges in personal communication services(PCS ) Is to locate many mobile terminals that nay move from place to place frequently. This kind of system operation is called location management. This task entails sophisticated signaling traffic and database queries. Several strategies have been proposed to improve the efficiency of location management. These strategies use location register databases to store the current locations of mobile terminals, and are vulnerable to failure of the location register databases. In this paper, we propose a fault-tolerant pointer forwarding scheme with distributed home location register in order to tolerate the failure of location registers. The performance of the proposed scheme is evaluated analytically by simulation, and Is compared with Biaz's bypass forwarding strategy and two-path forwarding strategy.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.200-208
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• 2000

Multi-ports register could shared several instructions at the same time in read operation. We address a formal methods for describing timing analysis and resource restriction in pipeline super scalar process that having multi-Port registers. First, we specify in-order pipeline instructions, and then, extend timing analysis in out-of-order super-scalar. In this case, we find instruction pairs in any cycle which can execute same time, We use ACSR(Algebra of Communicating Shared Resources), a branch of formal methods based on process algebra, for instruction specification and modelling.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.9 no.3
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• pp.85-93
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• 2010

This paper proposes a new dynamic hardware allocation and binding algorithm of a simultaneous allocation and binding for SOC design automation. The proposed algorithm works on scheduled input graph and simultaneously allocates binds functional units, interconnections and registers by considering interdependency between operations and storage elements in each control step, in order to share registers and interconnections connected to functional units, as much as possible. This paper shows the effectiveness of the proposed algorithm by comparing experiments to determine number of function unit in advance or by comparing separated executing allocation and binding of existing system.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.329-334
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• 2002

For the testability, this paper proposed the algorithm at autonomous synthesis which includes the data path structure as the self testing as possible on high level synthesis method when VHDL, coding is used in the system design area. In the proposed algorithm of this paper, MUXs and registers are assigned to the data path of designed system. And the designed data path could be mapped the H/W specification of described VHDL coding to the testable library. As a results, it was mapped H/W to the assign algorithm that is minimized MUX and the registers in collision graph.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.17-29
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• 1999

This paper presents a high level synthesis method targeting low power consumption for data-dominated CMOS circuits (e.g., DSP). The high level synthesis is divided into three basic tasks: scheduling, resource and register allocation. For lower power scheduling, we increase the possibility of reusing an input operand of functional units. For a scheduled data flow graph, a compatibility graph for register and resource allocation is formed, and then a special weighted network is then constructed from the compatibility graph and the minimum cost flow algorithm is performed on the network to obtain the minimum power consumption data path assignment. The formulated problem is then solved optimally in polynomial time. This method reduces both the switching activity and the capacitance in synthesized data path. Experimental results show 15% power reduction in benchmark circuits.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.166-171
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• 2003

In this paper, we propose a minimal power data path allocation algorithm for low power circuit design. The proposed algorithm minimizes switching activity for input variables in scheduled CDFG. Allocations are further divided into the tasks of register allocation and module allocation. The register allocation algorithm execute that it eliminate spurious switching activity in functional unit and minimize the numbers of multiplexer. Also, resource allocation method selects a sequence of operations for a module such that the switching activity is reduced. Therefore, the algorithm executes to minimize the switching activity of input values, sequence of operations and number of multiplexer. Experimental results using benchmarks show that power is reduction effect from 13% to 17% power consumption, when compared with the Genesis-lp high-level synthesis system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.3
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• pp.235-239
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• 1989

A multiplier is proposed for computing multiplication of two arbitrary elements in the finite fields GF($2^m$), and the operation process is described step by step. The modified type of the circuit which is constructed with m-stage feedgack shift register, m-1 flip-flop, m AND gate, and m-input XOR gate is presented by referring to the conventional shift-register multiplier. At the end of mth shift, the shift-register multiplier stores the product of two elements of GF($2^m$); however the proposed circuit in this paper requires m-1 clock times from first input to first output. This circuit is simpler than cellulra-array or systolic multiplier and moreover it is faster than systolic multiplier.