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A Dynamic Hardware Allocation and Binding Algorithm for SOC Design Automation  

Eom, Kyung-Min (세명대학교 대학원)
Lin, Chi-Ho (세명대학교 컴퓨터학부)
Publication Information
The Journal of The Korea Institute of Intelligent Transport Systems / v.9, no.3, 2010 , pp. 85-93 More about this Journal
Abstract
This paper proposes a new dynamic hardware allocation and binding algorithm of a simultaneous allocation and binding for SOC design automation. The proposed algorithm works on scheduled input graph and simultaneously allocates binds functional units, interconnections and registers by considering interdependency between operations and storage elements in each control step, in order to share registers and interconnections connected to functional units, as much as possible. This paper shows the effectiveness of the proposed algorithm by comparing experiments to determine number of function unit in advance or by comparing separated executing allocation and binding of existing system.
Keywords
Allocation; binding; register; functional unit; interconnection;
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1 R. Camposano, "From behavior to structure: high-level synthesis," IEEE Design & Test of Computer, vol. 7, no. 5, pp. 8-19, Oct. 1990.   DOI   ScienceOn
2 E. S. Kuh, and T. Ohtuski, "Recent advance in VLSI layout," Proc. IEEE, vol. 78, no. 2, pp. 237-263, Feb. 1990.   DOI   ScienceOn
3 S. Huang, C. Cheng, Y. Ni, and W. Yu, "Resister binding for clock period minimization," Proc. Design Automation Conf., pp. 439-444, July 2006.
4 L. Liu, T. Chou, A. Aziz, and D. F. Wong, "Zero-skew clock tree construction by simulataneous, wire sizing and buffer insertion," Proc. Int. Society for Peritoneal Dialysis, pp. 33-38, 2000.
5 K. Ravindran, A. Kuehlmann, and E. Sentovich. "Multi-domain clock skew scheduling," Proc. Int. Conf. Computer-Aided Design, pp. 801-805, Nov. 2003.
6 Q. Zhao, C. A. J. van Eijk, C. A. Alba Pinto, and J. A. G. Jess, "Register binding for predicated execution in dsp application," Proc. Int. Symp. Circuits and Systems, pp. 113-117, Sept. 2000.
7 E. S. Kuh, and T. Ohtuski, "Recent advance in VLSI layout," Proc. IEEE, vol. 78, no. 2, pp. 237-263, Feb. 1990.   DOI   ScienceOn
8 M. C. McFarl, A. C. Paker, and R. Camposano, "The high-level synthesis of the digital system," Proc. IEEE, vol. 8, no. 2, pp. 301-318, Feb. 1990.
9 D. G. Daniel , D. D. Nikil, and C. H. W. Allen, High-Level Synthesis : Introduction to Chip and System Design, Kluwer Academic Publishers, Boston, 1992.
10 J. R. Armstrong and F. G. Gray, Structured Logic Design with VHDL, Prentice-Hall, Inc., pp. 231-254, 1993.
11 P. Paulin, J. Knight, and E. Girczyc, "HAL: A multi-paradigm approach to automatic data path synthesis," Proc. Design Automation Conf., pp. 263-270, June 1986.
12 B. Pangrle, "Splicer : A heuristic approach to connectivity binding," Proc. Design Automation Conf., pp. 536-541, June 1988.