1 |
M. Poletto and V. Sarkar. "Linear Scan Register Allocation". ACM Trans. Program. Lang. Syst., Vol.21, pp.895-913, 1999.
DOI
ScienceOn
|
2 |
G.J. Chaitin, "Register Allocation and Spilling via Graph Coloring". In Proc. 1892 SIGPLAN Symp. on Compiler construction, pp.98-105, 1982.
|
3 |
EEMBC. Characterization of the EEMBC Benchmark Suite. http://eembc.org/benchmark/characterization.pdf.
|
4 |
GNU Compiler Collection, http://gcc.gnu.org
|
5 |
M.M. Brandis and H. Mossenbock. "Single-pass generation of static single-assignment form for structured languages". ACM Trans. Program. Lang. Syst., Vol.16, pp.1684-1698, 1994.
DOI
ScienceOn
|
6 |
C. Wimmer and H. Mossenbock. "Optimized interval splitting in a linear scan register allocator". In Proc. 1st ACM/USENIX int. conf. Virtual execution environments, pp.132-141, 2005.
|
7 |
L. Spracklen, Y. Chou, and S. G. Abraham. "Effective Instruction Prefetching in Chip Multiprocessors". In Proc. 11th Int. Symp. HPCA, pp.225-236, 2005.
|
8 |
S.P. Morse, W.B. Pohlman and B.W. Ravenel. "The Intel 8086 Microprocessor: a 16-bit Evolution of the 8080", IEEE Computer, Vol.11, pp.18-27, 1978.
|
9 |
E. Stritter and T. Gunter. "Microsystems a Microprocessor Architecture for a Changing World: The Motorola 68000", IEEE Computer, Vol.12, pp.43-52, 1979.
|
10 |
D.A. Patterson. "A performance evaluation of the Intel 80286", ACM SIGARCH Comput. Archit. News, Vol.10, pp.16-18, 1982.
DOI
|
11 |
H. Kim, D. Jung, H. Jung, Y. Choi, J. Han, B. Min, and H. Oh. "AE32000B: a Fully Synthesizable 32-Bit Embedded Microprocessor Core", ETRI Journal, Vol.25, pp.337-344, 2003.
DOI
ScienceOn
|