• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.159-161
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• 2018

지난 수년 간 다량으로 배출되고 있는 폐 배터리를 에너지 저장장치(ESS)로서 재활용하고자 하는 연구가 활발히 진행되고 있다. 이러한 ESS 시스템에는 사용하는 배터리마다의 규격이나 이전 사용 시 수명, 배출 시 상태의 차이가 존재하기 때문에 각 배터리 간 셀밸런싱 시스템이 필수로 요구된다. 현재까지 직렬형, 병렬형 등이 연구되고 있지만 모듈화나 신뢰성 등을 만족 시키기 위해서는 병렬형이 유리하다. 본 논문에서는 양방향 리니어 레귤레이터를 사용하며 셀 벨런싱 회로가 없는 병렬형 충방전 시스템을 제안하고자 한다.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.08a
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• pp.125-128
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• 2000

가상적인 검출잡음을 가정하고 칼만 필타(Kalman Filter)를 고려하여 근사적 최적 레귤레이터의 특성에 가깝게 함으로써 견실 안정성을 회복할 수 있는 제어 시스템의 설계에 관하여 검토한다. 본 연구에서는 관측기를 이용한 최적 레귤레이터 계에 적분기를 결합한 견실제어계의 설계법을 나타내고 견실성을 회복할 수 있는 제어기의 파라미터 설정법을 나타낸다. 제어대상의 파라미터 변동에 의해서 생기는 등가인 외란을 억제하고 과도특성이 변하지 않는 제어 시스템을 모델 매칭의 원리에 기초하여 설계한다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.4
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• pp.1222-1228
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• 2010

This paper presents a design of the CMOS LDO regulator with a fast transient response for a high speed PMIC(power management integrated circuit). Proposed LDO regulator circuit consists of a reference voltage circuit, an error amplifier and a power transistor. 2-stage wide-band OTA buffer between error amplifier and power transistor is added for a good output stability. Although conventional source follower buffer structure is simple, it has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide-band OTA instead of source follower structure for a buffer. From HSPICE simulation results using a $0.5{\mu}m$ CMOS standard technology, simulation results were 16 mV/V line regulation and 0.007 %/mA load regulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.1
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• pp.71-80
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• 2015

LDO(Low Drop-Out) regulators have become an essential building block in modern PMIC(Power Managment IC) to extend battery life of electronic devices. In this paper, we optimize capacitor-less LDO regulator via Geometric Programming(GP) designed using Dongbu HiTek $0.5{\mu}m$ BCDMOS process. GP-compatible models for stability and PSR of LDO regulators are derived based on monomial formulation of transistor characteristics. Average errors between simulation and the proposed model are 9.3 % and 13.1 %, for phase margin and PSR, respectively. Based on the proposed models, the capacitor-less LDO optimization can be performed by changing the PSR constraint of the design. The GP-compatible performance models developed in this work enables the design automation of capacitor-less LDO regulator for different design target specification.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.1
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• pp.37-44
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• 2021

In this study, shape design and material selection were carried out for a two-stage pressure-reducing regulator to compensate for the shortcomings of a one-stage mechanical decompression regulator. The shape of the contact surface of the depressurization unit was considered, material was selected, and the shape was designed to compensate for the pulsation and slow response through the two-stage decompression and to solve the problem of high pressure deviation. In terms of airtightness, the deformation amount of TPU showed a small amount of displacement of up to 15.82%. Considering the fact that it is applicable to various hydrogen fuel supply systems by securing universality by applying electronic solenoids to the second pressure reduction, magnetic materials were selected. The hydrogen embrittlement and corrosion resistance were evaluated to verify the plating process. Surface corrosion did not occur in only the case of Cr plating. The elongation during the corrosion process was compared using a tensile test, and there was a difference within 2%.

• Journal of IKEEE
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• v.21 no.2
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• pp.154-157
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• 2017

This paper proposes the Low-Dropout regulator with two output. Each of the two output has feedback, and shared feedback loop. PMOS is added to solve the problem the occur when sharing the feedback loop. Thus eased the Load Transient Response. Also Using one of the bias citcuit and one of the pass transistor, Area is reduce by half compared to Existing Area that used to obtain output of two output.

• Journal of IKEEE
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• v.24 no.2
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• pp.598-603
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• 2020

In this paper present a Low Drop-Out(LDO) regulator that improves load transient characteristics due to the push-pull pass transistor structure is proposed. Improved load over the existing LDO regulator by improving the overshoot and undershoot entering the voltage line by adding the proposed push-pull circuit between the output stage of the error amplifier inside the LDO regulator and the gate stage of the pass transistor and the push-pull circuit at the output stage. It has a delta voltage value of transient characteristics. The proposed LDO structure was analyzed in Samsung 0.13um process using Cadence's Virtuoso, Spectre simulator.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.1-6
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• 2016

In this paper, we introduce the characteristics of a vertical PNP transistor that improves start current by decreasing quiescent current with suppressing the parasitic transistor. In order to suppress the parasitic effect, we designed a vertical PNP transistor which suppresses parasitic PNP transistor by using the "DN+ links" without changing the circuit and made a LDO regulator using a standard IC processor. HFE of the fabricated parasitic PNP transistor decreased from conventional 18 to 0.9. Starting current of the LDO regulator made of the vertical PNP transistor using the improved "DN+ linked" structure is reduced from the conventional starting current of 90mA to 32mA. As the result, we developed a LDO regulator which consumes lower power in the standby state.

• Journal of IKEEE
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• v.25 no.3
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• pp.506-510
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• 2021

In this paper, we propose an LDO that improves the load regulation change due to the current detection structure. The proposed LDO regulator adds the proposed current detection circuit to the output stage. Thereby to improve the load regulation of the delta value coming in on the output has a voltage value of an improved load Regulation characteristics than conventional LDO regulator. Using the proposed current detection structure, it was possible to improve the output change according to the change of the load current by about 60%. The proposed circuit has been simulated and verified characteristics by using a Spectre, Virtuoso simulation of Cadence.

• Journal of IKEEE
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• v.23 no.2
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• pp.722-726
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• 2019

In this paper, we propose a low drop-out (LDO) regulator with improved power-supply rejection (PSR) characteristics in the high frequency region. In particular, an NMOS transistor with a high output resistance is added as a compensation circuit to offset the high frequency noise passing through the finite output resistance of the PMOS power switch. The elimination of power supply noise by the compensating transistor was explained analytically and presented as the direction for further improvement. The circuit was fabricated in a $0.35-{\mu}m$ standard CMOS process and Specter simulations were carried out to confirm the PSR improvement of 26 dB compared to the conventional LDO regulator at 10 MHz.