• Journal of Practical Engineering Education
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• v.14 no.2
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• pp.245-258
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• 2022

Computational thinking with programming skills has been widely emphasized for future industrial engineering researchers and practitioners in Industry 4.0. However, industrial engineering students still have limited opportunities to improve their computational thinking abilities during university coursework. In this regard, this research study proposes to use Python programming language for teaching classical Industrial Engineering subjects. For a specific case study, we designed and instructed an Engineering Economy lecture which cultivates the concept and techniques of economic analysis for engineering students. During the class, we introduced the usage of several Python libraries that include numpy-financial for basic financial functions, numpy and scipy for simple numerical computation and analysis, and matplotlib for data visualization. Anonymous class evaluation survey showed the effectiveness of the proposed teaching method in terms of both educational satisfaction and contents delivery. Finally, we found additional needs for providing lectures that adopt the similar teaching style to the proposed method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2A
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• pp.209-215
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• 2010

This paper describes a design of variable-length FFT/IFFT processor (VL_FCore) for OFDM-based multi-standard communication systems. The VL_FCore adopts in-place single-memory architecture, and uses a hybrid structure of radix-4 and radix-2 DIF algorithms to accommodate various FFT lengths in the range of $N=64{\times}2^k\;(0{\leq}k{\leq}7)$. To achieve both memory size reduction and the improved SQNR, a two-step conditional scaling technique is devised, which conditionally scales the intermediate results of each computational stage. The performance analysis results show that the average SQNR's of 64~8,192-point FFT's are over 60-dB. The VL_FCore synthesized with a $0.35-{\mu}m$ CMOS cell library has 23,000 gates and 32 Kbytes memory, and it can operate with 75-MHz@3.3-V clock. The 64-point and 8,192-point FFT's can be computed in $2.25-{\mu}s$ and $762.7-{\mu}s$, respectively, thus it satisfies the specifications of various OFDM-based systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.393-396
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• 2009

This paper describes a design of variable-length FFT/IFFT processor for OFDM-based communication systems. The designed FFT/IFFT processor adopts the in-place single-memory architecture, and uses a hybrid structure of radix-4 and radix-2 DIF algorithms to accommodate FFT lengths of $N=64{\times}2^k$ ($0{\leq}k{\leq}7$). To achieve both memory size reduction and the improved SQNR, a two-step conditional scaling technique is devised, which conditionally scales the intermediate results of each computational stage. The performance analysis results show that the average SQNR's of 64~8,192-point FFT's are over 60-dB. The processor synthesized with a $0.35-{\mu}m$ CMOS cell library can operate with 75-MHz@3.3-V clock, and 64-point and 8,192-point FFT's can be computed in $2.55-{\mu}s$ and $762.7-{\mu}s$, respectively, thus it satisfies the specifications of wireless LAN, DMB, and DVB systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.7
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• pp.1626-1633
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• 2010

In this paper, we implemented medicinal plant information system based on user requirement using Ajax technique which can retrieve data from the server asynchronously in the background without refresh webpage and jQuery which is a lightweight cross-browser javascript library. Also, we presented the source code handling the server response data used in the system and compared the features by the type of response data. This system shows the improvement of user interaction and response rates because of a simple response data from the server, client-side data processing and change of web page by manipulating the DOM tree and provides ease of use and convenient data access.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.355-362
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• 2013

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator, which adopts a pipelined architecture to improve throughput, performs arctangent operation using vectoring mode of CORDIC algorithm. Fixed-point MATLAB modeling and simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by FPGA-in-the-loop verification using MATLAB/Simulink, and synthesized with a TSMC 0.18-${\mu}m$ CMOS cell library. It has 16,000 gates and the estimated throughput is about 9.6 Gbps at 200Mhz@1.8V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.4
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• pp.821-827
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• 2009

Currently, with the development of web 2.0 knowledge sharing system became more and more important. In this paper, we proposed and implemented seminar assistant system using database system and knowledge sharing system on public seminar. We recorded speaker's voice and presentation files on our system and user can review past talks on our seminar review systems. Our database system is implemented using MS SQL, and Input/Output Completion Port(IOCP) socket model as our server side network module. Also we used presentation software using Direct Show with MFC and Windows Presentation Foundation(WPF). and our review system is based on WFP programmed with C# language.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.89-96
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• 2002

In this paper, the ADI(Adaptive De-interlacing) algorithm is proposed, which improves visually and subjectively horizontal and vertical edges of the image processed by the ELA(Edge Line-based Average) method. This paper also proposes a VLSI architecture for the proposed algorithm and the architecture designed through the full custom CMOS layout process. The proposed algorithm is verified using C and Matlab and implemented using $0.6{\mu}m$ 2-poly 3-metal CMOS standard libraries. For the circuit and logic simulation, Cadence tool is used.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.80-86
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• 2003

Elliptic curve cryptosystem(ECC) offers the highest security per bit among the known publick key system. The benefit of smaller key size makes ECC particularly attractive for embedded applications since its implementation requires less memory and processing power. In this paper, we propose a new multiplier structure with configurable output sizes and operation cycles. The number of output bits can be freely chosen in the new architecture with the performance-area trade-off depending on the application. Using the architecture, a 193-bit normal basis multiplier and inversion unit are designed in GF(2$^{m}$ ). It is implemented using HDL and 0.35${\mu}{\textrm}{m}$ CMOS technology and the operation is verified by simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.183-185
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• 2013

As mobile devices have developed, flash animations suitable for the existing web have solved part of the weakness caused by the image quality deterioration and the transmission capacity, but it is difficult to express 3D stereo-scopic images. Also, for the real time-randering of visual expressions for animation and the device technique for smartphone to accord with commercial demands, it is required to develop the 3D image processing technique. This paper studied on the image processing method for 3D animation capable of 3D graphic rendering with view system of android and OpenGL M3G in an embedded system device and OpenGL ES 2.0 library.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2154-2162
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• 2009

This paper describes a scalar multiplier for Elliptic curve cryptography for smart card security. The scaler multiplier has 163-bits key size which supports the specifications of smart card standard. To reduce the computational complexity of scala multiplication on finite field, the non-adjacent format (NAF) conversion algorithm which is based on complementary recoding is adopted. The scalar multiplier core synthesized with a 0.35-${\mu}m$ CMOS cell library has 32,768 gates and can operate up to 150-MHz@3.3-V. It can be used in hardware design of Elliptic curve cryptography processor for smartcard security.