• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.254-256
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• 2019

소수체 GF(p)와 이진체 $GF(2^m)$ 상의 다중 타원곡선을 지원하는 듀얼 필드 ECC (DF-ECC) 프로세서를 설계하였다. DF-ECC 프로세서의 저면적 설와 다양한 타원곡선의 지원이 가능하도록 워드 기반 몽고메리 곱셈 알고리듬을 적용한 유한체 곱셈기를 저면적으로 설계하였으며, 페르마의 소정리(Fermat's little theorem)를 유한체 곱셈기에 적용하여 유한체 나눗셈을 구현하였다. 설계된 DF-ECC 프로세서는 스칼라 곱셈과 점 연산, 그리고 모듈러 연산 기능을 가져 다양한 공개키 암호 프로토콜에 응용이 가능하며, 유한체 및 모듈러 연산에 적용되는 파라미터를 내부 연산으로 생성하여 다양한 표준의 타원곡선을 지원하도록 하였다. 설계된 DF-ECC는 FPGA 구현을 하드웨어 동작을 검증하였으며, 0.18-um CMOS 셀 라이브러리로 합성한 결과 22,262 GEs (gate equivalences)와 11 kbit RAM으로 구현되었으며, 최대 100 MHz의 동작 주파수를 갖는다. 설계된 DF-ECC 프로세서의 연산성능은 B-163 Koblitz 타원곡선의 경우 스칼라 곱셈 연산에 885,044 클록 사이클이 소요되며, B-571 슈도랜덤 타원곡선의 스칼라 곱셈에는 25,040,625 사이클이 소요된다.

• Journal of Mushroom
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• v.15 no.2
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• pp.78-83
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• 2017

Microsatellite SSR markers were developed and utilized to reveal the genetic diversity of 32 strains of Flammulina velutipes collected in Korea, China, and Japan. From the SSR-enriched library, 490 white colonies were randomly selected and sequenced. Among the 490 sequenced clones, 85 (17.35%) were redundant. Among the remaining 405 unique clones, 201 (49.6%) contained microsatellite sequences. We used 12 primer pairs that produced reproducible polymorphic bands for four diverse strains, and these selected markers were further characterized in 32 Flammulina velutipes strains. A total of 34 alleles were detected using the 12 markers, with an average of 3.42 alleles, and the number of alleles ranged from two to seven per locus. The major allele frequency ranged from 0.42 (GB-FV-127) to 0.98 (GB-FV-166), and values for observed ($H_O$) and expected ($H_E$) heterozygosity ranged from 0.00 to 0.94 (mean = 0.18) and from 0.03 to 0.67 (mean = 0.32), respectively. SSR loci amplified with GB-FV-127 markers gave the highest polymorphism information content (PIC) of 0.61 and mean allele number of five, whereas for loci amplified with GB-FV-166 markers these values were the lowest, namely 0.03 and two. The mean PIC value (0.29) observed in the present study with average number of alleles (3.42). The genetic relationships among the 32 Flammulina velutipes strains on the basis of SSR data were investigated by UPGMA cluster analysis. In conclusion, we succeeded in developing 12 polymorphic SSRs markers from an SSR-enriched library of Flammulina velutipes. These SSRs are presently being used for phylogenetic analysis and evaluation of genetic variations. In future, these SSR markers will be used in clarifying taxonomic relationships among the Flammulina velutipes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.41-49
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• 2008

This paper presents a design of the control block of a passive UHF RFID tag IC according to EPCglobal Class-1 Generation-2 UHF RFID 1.1.0 Protocol. The control block includes a PIE block, CRC5/CRC16, a Slot Counter, a Random Number Generator, a Main Control Block, a Encoder and a Memory Interface. The control block has been designed using the Verilog HDL and has been simulated. Functional simulation results for the overall control block operation show that 11 instructions with 7 states are operated correctly. Also, the control block has been implemented with 36,230 gates by Synopsys Design Compiler and Apollo using Magnachip 0.25$\mu$m technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.21-29
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• 2012

This paper presents optimized searching technique to improve the performance of H.264/AVC. By using the proposed forward and backward searching algorithm, redundant cycles of latency for data reordering can be removed. Furthermore, in order to reduce the total number of execution cycles of CAVLC encoder, early termination mode and two stage pipelined architecture are proposed. The experimental result shows that the proposed architecture needs only 36.0 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 57.8% than that of previous designs. The proposed CAVLC encoder was implemented using Verilog HDL and synthesized with Magnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 17K with 125Mhz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.87-95
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• 2009

In this paper, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed scalable FFT processor can support the variable length of 64, 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate4eve1 circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 59% and 39%, respectively, compared with those of the 4-channel radix-2 single-path delay feedback (R2SDF) FFT processor. Also, compared with 4-channel radix-2 MDC (R2MDC) FFT processor, it is confirmed that the gate count and memory size are reduced by 16.4% and 26.8, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4A
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• pp.414-422
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• 2011

This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of $96{\times}96$ in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of $4.34{\times}10^{-5}$ for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a $0.18{\mu}m$ CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.

• Proceedings of the Korea Water Resources Association Conference
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• 2018.05a
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• pp.135-135
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• 2018

한강의 잠수교는 평상시에는 사람과 차의 통행이 가능하나 예측수위가 5.5m일 경우, 보행자통제, 6.2m일 경우, 차량통제를 실시한다. 잠수교는 국토교통부의 홍수예보 지점은 아니지만 그 특수성으로 인해 정확한 홍수위 예측을 통해 선행시간을 확보할 필요가 있다. 일반적으로 하천 홍수위 예측을 위해서는 강우-유출 모형과 하도추적을 위한 수리모형을 결합한 모델링이 요구되나 잠수교는 하류부 조위로 인한 배수 및 상류부 팔당댐 방류량의 영향을 받아 물리적 수리 수문모형의 구축이 상당히 제약적이다. 이에 본 연구에서는 딥러닝 오픈 라이브러리인 Tensorflow 기반의 LSTM 심층신경망(Deep Neural Network) 모형을 구축하여 잠수교의 수위예측을 수행한다. LSTM 모형의 학습과 검증을 위해 2011년부터 2017년까지의 10분단위의 잠수교 수위자료, 팔당댐의 방류량과 월곶관측소의 조위자료를 수집한 후, 2011년부터 2016년까지의 자료는 신경망 학습, 2017년 자료를 이용하여 학습된 모형을 검증하였다. 민감도 분석을 통해 LSTM 모형의 최적 매개변수를 추정하고, 이를 기반으로 선행시간(lead time) 1시간, 3시간, 6시간, 9시간, 12시간, 24시간에 대한 잠수교 수위를 예측하였다. LSTM을 이용한 1~6시간 선행시간에 대한 수위예측의 경우, 모형평가 지수 NSE(Nash-Sutcliffe Efficiency)가 1시간(0.99), 3시간(0.97), 6시간(0.93)과 같이 정확도가 매우 우수한 것으로 분석되었으며, 9시간, 12시간, 24시간의 경우, 각각 0.85, 0.82, 0.74로 선행시간이 길어질수록 심층신경망의 예측능력이 저하되는 것으로 나타났다. 하천수위 또는 유량과 같은 수문시계열 분석이 목적일 경우, 종속변수에 영향을 미칠 수 있는 가용한 모든 독립변수를 데이터화하여 선행 정보를 장기적으로 기억하고, 이를 예측에 반영하는 LSTM 심층신경망 모형은 수리 수문모형 구축이 제약적인 경우, 홍수예보를 위한 활용이 가능할 것으로 판단된다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.18-26
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n wireless LAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. From fixed-point modeling and Matlab simulations for various bit-widths, decoding performance and optimal hardware parameters such as fixed-point bit-width are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18-${\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1183-1190
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• 1999

This paper presents an efficient hardware architecture to improve the frame memory interface occupying the largest hardware area together with motion estimator in implementing MPEG-2 video encoder as an ASIC chip. In this architecture, the memory size for internal data buffering and hardware area for frame memory interface control logic are reduced through the efficient memory map organization of the external SDRAM having dual bank and memory access timing optimization between the video encoder and external SDRAM. In this design, 0.5 m, CMOS, TLM (Triple Layer Metal) standard cells are used as design libraries and VHDL simulator and logic synthesis tools are used for hardware design add verification. The hardware emulator modeled by C-language is exploited for various test vector generation and functional verification. The architecture of the improved frame memory interface occupies about 58% less hardware area than the existing architecture[2-3], and it results in the total hardware area reduction up to 24.3%. Thus, the (act that the frame memory interface influences on the whole area of the video encoder severely is presented as a result.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1355-1362
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.