• Journal of Astronomy and Space Sciences
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• v.19 no.4
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• pp.293-304
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• 2002

This paper describes the re-design and the calibration results of the MAG digital circuit onboard the KSR-3. We enhanced the sampling rate of magnetometer data. Also, we reduced noise and increased authoritativeness of data. We could confirm that AIM resolution was decreased less than InT of analog calibration by a digital calibration of magnetometer. Therefore, we used numerical-program to correct this problem. As a result, we could calculate correction and error of data. These corrections will be applied to magnetometer data after the launch of KSR-3.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.799-804
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• 2012

To converter time information to digital information Time-to-Digital Converter(TDC) is designed by using analog delay elements. To obtain the temperature stable characteristics the circuit is designed and the operation of the designed circuit is confirmed by HSPICE. The characteristics variation of the designed delay element with temperature is from -0.18% to 0.126% compared to room temperature characteristics when the temperature is varied from $-20^{\circ}C$ tp $70^{\circ}C$. Time difference is from -0.18% to 0.12% compared to room temperature characteristic when the temperature is varied from $-20^{\circ}C$ tp $70^{\circ}C$. The time difference is simulated when the digital output is 15. However the time difference is from -1.09% to 1.28% in the TDC using temperature non-stable analog delay elements.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.671-672
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• 2011

Time to digital converter is designed. To obtain the digital signal from time information the analog delay element is used. Because the analog delay element shows more stable characteristics compared to the digital delay element in view point of process variation. The designed circuit has temperature stale characteristics when the range of operating temperature is from $-20^{\circ}C$ to $70^{\circ}C$. The circuit is simulated and confirmed by HSPICE.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.91-97
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• 2004

A digital over-sampling noise-shaping coder to achieve the processing accuracy for the audio signal bandwidth is designed. In order to implement an optimized design of the noise-shaping coder as a form of U (intellectual property), circuit design techniques that optimize the multiplication and the ROM architectures are proposed with emphasis on the low-voltage operation under 2.0 V and the minimization of the hardware resources. In the design and verification methodology, the overall architectures and the internal bit width have been determined through behavioral simulations. The overall performances including timing margin have been estimated through transistor-level simulations. Furthermore, the test results of the implemented chip using a 0.35-${\mu}{\textrm}{m}$ standard CMOS process proposed the validity of the proposed circuits and the design methodology.

• ICROS
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• v.17 no.4
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• pp.35-41
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• 2011

비동기적으로 동작하는 디지털 회로는 동기 순차 회로에 비해서 고속, 저전력 소비 등 여러 가지 장점을 지니기 때문에 현대 디지털 시스템에서 여전히 중요한 요소로 사용되고 있다. 본 기고에서는 비동기 순차 회로에서 발생하는 고장을 진단하고 극복하는 최신 기술을 소개한다. 본 기고에서 주로 다루는 기술은 '교정 제어'로서 피드백 제어의 원리를 이용하여 비동기 순차 회로의 안정 상태를 바꾸는 기법이다. 크리티컬 레이스(critical race), 무한 순환 등 비동기 회로 설계상의 오류를 포함하여 SEU(Single Event Upset), 총이론화선량(TID)에 의한 고장 등 외부 환경에 의해서 발생하는 비동기 회로의 고장을 교정 제어를 이용하여 진단하고 극복하는 기술에 대해서 알아본다.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.04b
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• pp.1121-1124
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• 2001

웹기반 학습은 학습자의 자율적인 통제하에서 학습이 이루어지는 특성을 갖고 있다. 학습 컨텐츠와 학습자간의 충분한 대화 즉, 상호작용이 제공되지 않는다면 학습자는 일방적인 학습을 수행하게 되므로 학습에 대한 정확한 이해를 판단할 수가 없다. 이런 문제점을 해결하기 위해서 웹기반 학습의 여러 유형의 컨텐츠중에서 가장 상호작용 요소가 강한 시뮬레이션 형태의 컨텐츠를 이용해서 디지털 회로를 직접 학습자가 설계할 수 있도록 웹기반 시뮬레이션 도구를 설계 및 구현하고자 한다. 이로 인해서 학습자와 학습 컨텐츠간의 쌍방향 대화를 할 수 있는 환경을 제공함으로써 복잡한 디지털 회로에 대한 학습자의 학습 결과에 대한 피드백을 줌으로써 학습자의 학습 성취도를 높일 수 있다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.156-157
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• 2014

본 논문에서는 저전력 12비트 1MSps 연속 근사형 레지스터 아날로그-디지털 변환기를 제안한다. 제안하는 회로는 1.8V의 공급 전압에서 동작하며, Magnachip/SK Hynix $0.18{\mu}m$ CMOS 1Poly-6Metal 공정을 이용하여 설계하였다. 입력신호의 주파수가 100kHz일 때, 설계된 회로는 3.24mW의 낮은 소비전력 특성, $0.56mm^2$의 작은 칩 면적 특성, 70.03dB의 SNDR(Signal-to-Noise Distortion Ratio) 및 11.34비트의 ENOB(Effective Number of Bits) 특성을 보였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.57-65
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• 2014

This paper presents a framework that is based on a reconfigurable macro-model of current-mode logic (CML) high-speed digital circuits enabling equation-based design optimization. The proposed macro-model is compatible with geometric programming, thereby enabling constraint-driven top-level power optimization. The proposed optimization framework is applied to a design of CML based serial-link transmitter with user-defined design specifications as an example of high speed digital circuits using 45nm and 90nm CMOS technology. The proposed optimization framework can derive a design with optimal power efficiency for given transistor technology nodes.

• Journal of Practical Engineering Education
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• v.16 no.4
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• pp.481-489
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• 2024

The purpose of this study is to propose a new teaching method of the digital logic circuit so that students can cultivate digital literacy in diversifying future educational environments. In this paper, we analyzed the previous studies related to teaching methods for Tinkercad and digital logic circuits and suggested how to apply Tinkercad to the specific instruction design of the digital logic circuit. In addition, after showing the class design using Tinkercad to the actual lessons, It turns out two significant facts in a survey: to create a circuit that can implement the operation of the basic gate and to make it easier to understand the principles of the basic gate. The teaching method suggested in this study can be informative for students to acquire basic knowledge of electricity and electronics. Since Tinkercad is an open software based on cloud systems that are used not only in Korea but also foreign countries, it can be utilized in the lessons of digital logic circuits in the near future.

• Journal of IKEEE
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• v.16 no.1
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• pp.20-27
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• 2012

In order to overcome jamming, a hysteresis tunable monolithic comparator circuit based on a 0.35 ${\mu}m$ CMOS process is suggested, designed, fabricated, measured and analyzed in this paper. To tune the threshold voltage of the hysteresis in the comparator circuit, two external digital bits are used with supply voltage of 3.3V. An improved variable hysteresis comparator circuit controlled by serial digital bits is suggested, designed and simulated to overcome jamming in modern warfare.