• Journal of KIISE:Computer Systems and Theory
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• v.35 no.5
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• pp.231-236
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• 2008

This paper proposes a cost-efficient and flexible FPGA-based logic circuit emulation platform. By improving the performance and adding more features, this new platform is an enhanced version of our LAPG. It consists of an FPGA-based hardware engine and software element to drive the emulation and monitor the results. It also provides an interactive verification environment which uses an efficient communication protocol through a bi-directional serial link between the host and the FPGA board. The experimental results show that this new approach saves $55%{\sim}99%$ of communication overhead compared with other methods. According to the test results, the new LAPG is more area efficient in complex circuits with many I/O ports.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.65-72
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• 2013

This paper presents design methodology for Memristor-CMOS circuits and its application to primitive IPs design. We proposed a Memristor model and designed basic elements, Memristor AND/OR gates. The primitive IPs based on a Memristor-CMOS technology is proposed for a Memristive system design. The netlists of IPs are extracted from the layouts of Memristor-CMOS and is verified with SPICE-like Memristor model under $0.18{\mu}m$ CMOS technology. As a result, an example design Memristor-CMOS full adder has only 47.6 % of silicon area compare to the CMOS full-adder.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.989-998
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• 2012

A ratio type of capacitance measurement circuit is proposed to measure an extremely small value of the fF capacitance on this paper. This measurement circuit is formed with a switched-capacitor integrator, a comparator, and logic circuit blocks to control the switches. It converts the measured ratio value between the known value of on-chip capacitor and the unknown value of capacitor to the digital signal. The fF capacitance with minimized error can be obtained by calculating this ratio. This proposed circuit is designed with standard CMOS $0.18{\mu}m$ process, and various HSpice simulations prove that this capacitance measurement circuit is able to measure the capacitance under 5fF with less than ${\pm}0.3%$ error rate.

• 전자공학회논문지 IE
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• v.45 no.3
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• pp.5-12
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• 2008

We propose efficient scan testing method capable of reducing the test data and power dissipation for digital logic circuits. The proposed testing method is based on a hybrid run-length encoding which reduces test data storage on the tester. We also introduce modified Bus-invert coding method and scan cell design in scan cell reordering, thus providing increased power saving in scan in operation. Experimental results for ISCAS'89 benchmark circuits show that average power of 96.7% and peak power of 84% are reduced on the average without fault coverage degrading. We have obtained a high reduction of 78.2% on the test data compared the existing compression methods.

• 한국정보교육학회:학술대회논문집
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• 2007.08a
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• pp.179-184
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• 2007

로봇교육은 여러 전자부품, 회로 등의 기계, 공학적인 교육뿐만 아니라 컴퓨터 프로그래밍, 디지털 기초 등의 컴퓨터 관련 교육까지 경험할 수 있다는 점에서 교육적 가능성과 활용가지가 매우 높다. 지금까지 단순한 기술 습득에 치중한 컴퓨터교육에 있어서, 알고리즘 및 프로그래밍 등의 창의력과 논리적인 문제해결력 향상을 중심으로 한 로봇교육은 정보과학영재교육에서 매우 중요하다고 할 수 있다. 본 연구에서는 정보과학영재교육의 특징을 분석하고 정보과학영재의 창의성을 키우기 위한 로봇교육과정을 개발하였다.

• Progress in Superconductivity and Cryogenics
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• v.8 no.1
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• pp.26-28
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• 2006

The development technique of digital logic using CMOS device is close reached several limitations These make technical needs that are ultra high speed superconductive systems based on CMOS silicon digital computing technique. Comparing digital logic based on silicon CMOS, the computing technique based on ultra high speed superconductive systems has many advantages which are ultra low power consumption, ultra high operation speed. etc. It is estimated that features like these increasingly improve the possibility of ultra low power and ultra superconductive systems. In this paper digital logics of current CMOS technique and RSFQ superconductive technique are compared with and analyzed.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.1-8
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• 1990

We made a 12-Laser Diode Array consisting of 12 Graded Index Separate Confinement (GRINSCH) InGaAs/Inp Buried Heterostructure 4 Quantum Well Laser Diodes and examined the potential of controlling lasing operation of each laser diode by the voltage to its electroabsorption region. Using Si V-Groove with 12 V-grooves, a 12-Laser Diode Array, and 12 optical fibers, we investigated the various characteristics of each laser diode by changing the voltage to its electro-absorption region. Finally, we thought over the promising way of implementing optical local area communication between electric circuit boards or between subscribers and a central office using a 12-Laser Diode Array, Si V-groove, and optical fibers.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.2
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• pp.17-28
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• 2002

Recently, the study on non-linear equalization, self-recovering equalization using the neural Network structure or Fuzzy logic, is lively in progress. In this thesis, if the value of error difference is large, coefficient adaptation rate is bigger, and if being small, it is smaller. We proposed the new FSG(Fuzzy Stochastic Gradient)/CMA algorithm combining TS(Tagaki-Sugeno) fuzzy model having fast convergence rate and low mean square error(MSE) and CMA(Constant Modulus Algorithm) which is prone to ISI and insensitive to phase alteration. As a simulation result of the designed channel adaptive equalizer using the proposed FSG/CMA algorithm, it is shown that SNR is improved about 3.5dB comparing to the conventional algorithm. 

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.10
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• pp.1063-1073
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• 1992

This paper deals with a method for extracting picture signals from CD graphics with a conventional CD player, schemes for designing circuits for the effective extraction of control signals, and the implementation of such circuits using commercially available logic components, thereby achieving cost-effectiveness. This paper also presents an implementation and evaluation of the CD-G system, which requires extracting picture signals, deinterleaving the extracted signals and analyzing control commands and displaying them on a screen. The CD-G system implemented using the extraction circuit presented herein has been observed to operate well in real time.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.6
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• pp.500-509
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• 2007

In this paper, we propose a novel pc-based 8-channel USB interface digital multi-controller (DMC) has capacity to be able to adjust ultrasonic motor's (USM's) the parameters-frequency, amplitude, phase difference using FPGA. The proposed DMC can control parameters directly by digital logic through a FPGA. Since it has counter circuit for rotary encoder to measure position and velocity of USM, the other separate circuits are unnecessary. Therefore, it could reduce the size of controller and the production cost. Finally, to verify the performance of proposed DMC, we tested the speed characteristic of two types USM with no-load as adjusting the parameters.