• Journal of the Korean BIBLIA Society for library and Information Science
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• v.14 no.1
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• pp.5-24
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• 2003

In recent years, electronic technologies are rapidly changing the library's approach to collection management. In digital age, collection is a hybrid, that is, a mix of analog materials and digital information resources. But electronic publications are both a blessing and a curse for libraries. And the rapid acceptance of electronic resources raises many misconceptions and myths about their capabilities. This paper analyzes the digital paradox of current collection management from six standpoints : production of digital informations : digital scholarly communication : digital access paradigm : acceptance of e-journal package web collection development : digital archiving. Nowadays the pragmatic view of library is a logical information gateway to its own services and those of other libraries and information providers. Libraries and librarians need a concept and strategies of the hybrid collection management that reflects digital reality.

• Journal of the Korea Computer Industry Society
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• v.2 no.9
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• pp.1183-1190
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• 2001

In this paper, it used a different pipeline method from conventional method which is encoding the video signal of analog with digital. It designed with pipeline structure of 4 phases as the pixel clock ratio of the whole operation of the encoder, and secured the stable operational timing of the each sub-blocks, it was visible the effect which reduces a gate possibility as designing by the ROM table or the shift and adder method which is not used a multiplication flag method of case existing of multiplication of the fixed coefficient. The designed encoder shared with the each sub-block and it designed the FPGA using MAX+PLUS2 with VHDL.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.768-771
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• 2007

Recently, Nand flash memory is widely used for digital equipments and its capacity and performance are rapidly improving. The limit on the number of writings and readings to/from Nand flash memory does not guarantee the integrity of its data. Therefore, ECC algorithm should be applied to the Nand flash controller. To reduce the access time, we use the look-up table to implement the ECC algorithm instead of the conventional logic gates.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.65-72
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• 2013

This paper presents design methodology for Memristor-CMOS circuits and its application to primitive IPs design. We proposed a Memristor model and designed basic elements, Memristor AND/OR gates. The primitive IPs based on a Memristor-CMOS technology is proposed for a Memristive system design. The netlists of IPs are extracted from the layouts of Memristor-CMOS and is verified with SPICE-like Memristor model under $0.18{\mu}m$ CMOS technology. As a result, an example design Memristor-CMOS full adder has only 47.6 % of silicon area compare to the CMOS full-adder.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2002.11a
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• pp.63-68
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• 2002

JPEG2000은 기존의 정지영상압축부호화 방식에 비해 우수한 비트율-왜곡(Rate-Distortion)특성과 향상된 주관적 화질을 제공하며 인터넷, 디지털 영상카메라, 이동단말기, 의학영상 등 다양한 분야에서 적용될 수 있는 새로운 정지영상압축 표준이다. 본 논문에서는 SoC(System on a Chip)설계를 고려한 JPEG2000 인코더의 구조를 제안하고 IP(Intellectual Property)를 설계 및 검증하였다. 구현된 JPEG2000 IP는 DWT(Discrete Wavelet Transform)블록, 스칼라양자화블록, EBCOT(Embedded Block Coding with Optimized Truncation)블록으로 구성되어 있다. IP는 모의실험을 통해 구현 구조에 대한 타당성을 검증하였고, 반도체설계자산연구센터에서 제시한 'RTL Coding Guideline'에 따라 HDL을 설계하였다. 특히, DWT블록은 구현시 많은 연산과 메모리 용량이 필요하므로 영상을 저장할 외부 메모리를 사용하였고, 빠른 곱셈과 덧셈연산을 위한 3단 파이프라인 부스곱셈기(3-state pipeline booth multiplier)와 캐리예측 덧셈기(carry lookahead adder)를 사용하였다. 설계된 JPEG2000 IP들은 삼성 0.35$\mu\textrm{m}$ 라이브러리를 이용하여 Synopsys사 Design Analyzer 틀을 통해 논리 합성하였으며, Xillinx 100만 게이트 FPGA칩에 구현하여 그 동작을 검증하였다. 또한, Hard IP 설계를 위해 Avanti사의 Apollo툴을 이용하여 Layout을 수행하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.11a
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• pp.493-496
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• 2002

홈 네트워크의 문제점인 IP 부족 문제와 부가 서비스(디지털 컨텐츠의 지능형 서비스, 서비스 번들 지원 등) 제공의 한계성을 극복하기 위해 Service Server for Residential Gateway(SSRG)를 제안한다. SSRG는 단독주택뿐만 아니라 대규모 아파트 단지 혹은 주택단지에 개별적으로 설치된 RG를 통합 관리하는 서버로서 홈 네트워크 및 내부 네트워크에 로컬 IP를 부여하고 RG와 SSRG를 NAT(Network Address Translator)를 통하여 제어함으로써 P의 문제를 해결함과 동시에 각 홈 네트워크와 RG의 기능을 확대하고 보다 많은 부가 서비스를 제공할 수 있도록 구현하였다. 제안된 SSRG는 가정 내에 보다 확장된 서비스와 기기 관리를 위한 통로 제공, RG 및 각종 기기들의 소프트웨어 업그레이드 및 기기 상태점검이 가능하고, 또한 사설 IP 상에서도 기기들을 외부에서 액세스 할 수 있고 각종 서버를 하나의 단지 혹은 논리적으로 구분되는 하나의 서브 넷에 두게 됨으로써 관리 및 향후 보수가 용이한 장점이 있다.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.1
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• pp.144-152
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• 1996

In this paper, a pulse-mode digital multilayer neural network with a massively parallel yet compact and flexible network architecture is presented. Algebraicneural operations are replaced by stochastic processes using pseudo-random pulse sequences and simple logic gates are used as basic computing elements. The distributions of the results from the stochastic processes are approximated using the hypergeometric distribution. A statistical model of the noise(error) is developed to estimate the relative accuracy associated with stochastic computing in terms of mean and variance. Numerical character recognition problems are applied to the network to evaluate the network performance and to justify the validity of analytic results based on the developed statistical model. The network architectures are modeled in VHDL using the mixed descriptions of gate-level and register transfer level (RTL). Experiments show that the statistical model successfully predicts the accuracy of the operations performed in the network and that the character classification rate of the network is competitive to that of ordinary Back-Propagation networks.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.131-137
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• 2013

The barrel distortion makes serious problems in a wide-angle camera employing a lens of a short focal length. This paper presents a low-complexity hardware architecture for a real-time barrel distortion corrector and its implementation. In the proposed barrel distortion corrector, the conventional algorithm is modified so that the correction is performed incrementally, which results in the reduction of the number of required hardware modules for the distortion correction. The proposed barrel distortion corrector has a pipelined architecture so as to achieve a high-throughput correction. The correction rate is 74.86 frames per sec at the operating frequency of 314MHz in a $0.11{\mu}m$ CMOS process, where the frame size is $2048{\times}2048$. The proposed barrel distortion corrector is implemented with 14.3K logic gates.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.56-65
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• 2006

The Quantum-dot Cellular Automata (QCA) can be considered as a candidate for the next generation digital logic implementation technology due to their small feature sizes and ultra low power consumption. Up to now, several designs using Uh technology have been proposed. However, we found not all of the designs function properly. Furthermore, no general design guidelines have been proposed so far. A straightforward extension of a simple functional design pattern may fail. This makes designing a large scale circuits using QCA technology an extremely time-consuming process. In this paper, we show several critical vulnerabilities related to unbalanced input paths to QCA gates and sneak noise paths in QCA interconnect structures. In order to make up the vulnerabilities, a disciplinary guideline will be proposed. Also, we present a fast adder which has been designed by the discipline, and verified to be functional by the simulation.