• Journal of Korea Multimedia Society
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• v.12 no.11
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• pp.1563-1571
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• 2009

In this paper, we propose a new boundary matching method for the temporal error concealment and a post processing algorithm for perceptual quality improvement of the concealed frame. Temporal error concealment is a method that substitutes error blocks with similar blocks from the reference frame. In conventional H.264/AVC standard, it compares outside pixels of erroneous block with inside pixels of reference block to find the most similar block. However, it is very possible that the conventional method substitutes erroneous block with the wrong one because it compares only narrow spatial range of pixels. In this paper, for substituting erroneous blocks with more correct blocks, we propose enhanced boundary matching method by comparing inside and outside pixels of reference block with outside pixels of erroneous block and setting up additional candidate motion vector in the fixed search range based on maximum and minimum value of candidate motion vectors. Furthermore, we propose a post processing method to smooth edges between concealed and decoded blocks without error by using the modified deblocking filter. We identified that the proposed method shows quality improvement of about 0.9dB over the conventional boundary matching methods.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.5
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• pp.151-161
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• 2009

Audio Video Standard (AVS) is the audio and video compression standard that was developed for domestic video applications in China. AVS employs low complexity tools to minimize degradation of RD performance of the state-the-art video codec, H.264/AVC. The AVS video codec consists of $8{\times}8$ block prediction and the same size transform to improve compression efficiency for VGA and higher resolution sequences. Currently, the AVS has been adopted more and more for IPTV services and mobile applications in China. So, many consumer electronics companies and multimedia-related laboratories have been developing applications and chips for the AVS. In this paper, we implemented the AVS video decoder and optimize it on TI's Davinci EVM DSP board. For improving the decoding speed and clocks, we removed unnecessary memory operations and we also used high-speed VLD algorithm, linear assembly, intrinsic functions and so forth. Test results show that decoding speed of the optimized decoder is $5{\sim}7$ times faster than that of the reference software (RM 5.2J).

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.3
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• pp.64-73
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• 2008

In this paper, we propose a novel objective video quality assessment method from encoded H.264/AVC.. Conventional algorithms have been proposed to assess video/image quality with image frames reconstructed in a decoder side. On the other hand, the proposed assessment is conducted with the syntax elements which are embedded in a bitstream. The proposed BS-based algorithm makes use of the statistics of boundary strength(BS) which are employed in the H.264/AVC. The proposed algorithm has lower computational complexity than conventional methods, EPSNR and Blockiness, resulting that it can accomplish assessment of the video quality in real time. Furthermore, the accuracy of the proposed video quality assessment is about 32% and 65% better than several conventional algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.37-42
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• 2008

In H.264/AVC decoder, intra predictor, motion compensator, and deblocking filter need to read reference images in external frame memory in decoding process. They read external frame memory very frequently, which lowers system operation speed and increases power consumption. This paper proposes a intra predictor integrated with motion compensator without external frame memory. It achieves power reduction and memory bandwidth minimization by exploiting data reuse of common and repetitive pixels. The proposed infra predictor achieves more than $45%\;{\sim}\;75%$ cycle time reduction compared with conventional intra predictors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.71-78
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• 2008

In this paper, we implement the H.264/AVC baseline decoder by hardware-software partitioning under the embedded Linux Kernel 2.4.26 and the FPGA-based target board with ARM926EJ-S core. We design several IPs for the time-demanding blocks, such as motion compensation, deblocking filter, and YUV-to-RGB and they are communicated with the host through the AMBA bus protocol. We also try to minimize the number of memory accesses between IPs and the reference software (JM 11.0) which is ported in the embedded Linux. The proposed IPs and the system have been designed and verified in several stages. The proposed system decodes the QCIF sample video at 2 frame per second when 24MHz of system clock is running and we expect the bitter performance if the proposed system is designed with ASIC.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.5
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• pp.12-19
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• 2007

This paper presents an ASIP(Application Specific Instruction Set Processor) for implementation of H.264/AVC, called VSIP(Video Specific Instruction-set Processor). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has hardware accelerators for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. The proposed VSIP can efficiently perform in real-time video processing and it can support various profiles and standards.