Browse > Article

Embedded SoC Design for H.264/AVC Decoder  

Kim, Jin-Wook (R&D Software Team, GS Instruments)
Park, Tae-Geun (Information, Communications, and Electronics Engineering, The Catholic University of Korea)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.9, 2008 , pp. 71-78 More about this Journal
Abstract
In this paper, we implement the H.264/AVC baseline decoder by hardware-software partitioning under the embedded Linux Kernel 2.4.26 and the FPGA-based target board with ARM926EJ-S core. We design several IPs for the time-demanding blocks, such as motion compensation, deblocking filter, and YUV-to-RGB and they are communicated with the host through the AMBA bus protocol. We also try to minimize the number of memory accesses between IPs and the reference software (JM 11.0) which is ported in the embedded Linux. The proposed IPs and the system have been designed and verified in several stages. The proposed system decodes the QCIF sample video at 2 frame per second when 24MHz of system clock is running and we expect the bitter performance if the proposed system is designed with ASIC.
Keywords
H.264/AVC; ARM;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Hae-Yong Kang, Kyung-Ah Jeong, Jung-Yang Bae, Young-Su Lee and Seung-Ho Lee. "MPEG4 AVC/H.264 Decoder with Scalable Bus Architecture and Dual Memory Controller," IEEE International Symposium on Circuits and Systems, vol.2, pp.145-148, 2004
2 Yang Kun, Zhang Chun, Du Guoze, Xie Jiangxiang and Wang Zhihua, "A Hardware-Software Co-design for H.264/AVC Decoder," IEEE Asian Solid-State Circuits Conference, pp.119-122, 2006
3 Seongmo Park, Hanjin Cho, Heebum Jung and Dukdong Lee, "An Implemented of H.264 Video Decoder using Hardware and Software," Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, pp.271-275. 2005
4 ITU, H.264/AVC Reference Software, http://iphome.hhi.de/suehring/tml, ver.JM11.0
5 Iain E. G. Richardson, "H.264 and MPEG-4 Video Compression Video Coding for Next-generation multimedia," John Willey & Sons, 2003
6 Dajiang Zhou and Peilin Liu, "A Hardware- Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264," IEEE International Symposium on Circuits and Systems, pp.2910-2913, 2007
7 ITU-T Recommendation H.264: Advanced video coding, ITU, 2004
8 채수익, 박상규, "SoCBase 플랫폼 아키텍쳐 설명서," 서울대학교 SoC 설계기술사업단, 2004
9 Yang Song, Zhenyu Liu, Goto Satoshi and Ikenaga Takeshi, "A VLSI architecture for motion compensation interpolation in H.264/AVC," IEEE 6th International Conference On ASIC(ASICON 2005), vol.1, pp.279-282, 2005