• The Journal of the Acoustical Society of Korea
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• v.22 no.2
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• pp.121-128
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• 2003

Acoustic Echo Cancellation(m) is very active research topic having many applications like teleconference and hands-free communication and it employs Double Talk Detector(DTD) to indicate whether the near-end speaker is active or not. However. the DTD is very sensitive to the variation of acoustical environment and it sometimes provides wrong information about the near-end speaker. In this paper, we are focusing on the development of robust DTD algorithm which is a basic building block for reliable AEC system. The proposed AEC system consists of delayless subband AEC and narrow-band DTD. Delayless subband AEC has proven to have excellent performance of echo cancellation with a low complexity and high convergence speed. In addition, it solves the signal delay problem in the existing subband AEC. On the other hand, the proposed narrowband DTD is operating on low frequency subband. It can take most advantages from the narrow subband such as a low computational complexity due to the down-sampling and the reliable DTD decision making procedure because of the low-frequency nature of the subband signal. From the simulation results of the proposed narrowband DTD and wideband DTD, we confirm that the proposed DTD outperforms the wideband DTD in a sense of removing possible false decision making about the near-end speaker activity.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.14-25
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• 1999

The IEEE standard 1149.1, which was proposed to increase the observability and the controllability in I/O pins, makes it possible the board level testing. In the boundary-scan environments, many shift operations are required due to their serial nature. This increases the test application time and the test application costs. To reduce the test application time, the method based on the parallel opereational multiple scan paths was proposed, but this requires the additional I/O pins and the internal wires. Moreover, it is difficult to make the designs in conformity to the IEEE standard 1149.1 since the standard does not support the parallel operation of data shifts on the scan paths. In this paper, the multiple scan path access algorithm which controls two scan paths simultaneously with one test bus is proposed. Based on the new algorithm, the new algorithm, the new board level BIST architecture which has a relatively small area overhead is developed. The new BIST architecture can reduce the test application time since it can shift the test patterns and the test responses of two scan paths at a time. In addition, it can reduce the costs for the test pattern generation and the test response analysis.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.13-22
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• 2010

This paper proposed the dual-loops multiphase DLL based mixed VCO/VCDL for a high frequency phase noise suppression of the input clock and the multiple frequencies generation with a precise duty cycle. In the proposed architecture, the dual-loops DLL uses the dual input differential buffer based nMOS source-coupled pairs at the input stage of the mixed VCO/VCDL. This can easily convert the input and output phase transfer of the conventional DLL with bypass pass filter characteristic to the input and output phase transfer of PLL with low pass filter characteristic for the high frequency input phase noise suppression. Also, the proposed DLL can correct the duty-cycle error of multiple frequencies by using only the duty-cycle correction circuits and the phase tracking loop without additional correction controlled loop. At the simulation result with $0.18{\mu}m$ CMOS technology, the output phase noise of the proposed DLL is improved under -13dB for 1GHz input clock with 800MHz input phase noise. Also, at 1GHz operating frequency with 40%~60% duty-cycle error, the duty-cycle error of the multiple frequencies is corrected under $50{\pm}1%$ at 2GHz the input clock.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.16-21
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• 2007

CMOS variable gain amplifier (VGA) IC designs for the structure monitoring systems of the telemetries were developed. A three stage cascaded VGA using a differential amplifier and a linear-in-dB controller is presented. A proposed VGA is a modified version of a conventional VGA such that the gain is controlled in a linear-in-dB fashion through the current ratio. The proposed VGA circuit introduced in this paper has a dynamic range of 77 dB with 1.5 dB gain steps. It also achieved a gain error of less than 1.5 dB over 77 dB gain range. The VGA can operate up to 10MHz dissipating 13.8 mW from a single 1.8 V supply. The core area of the VGA fabricated in a Magnachip $0.18{\mu}m$ standard CMOS process was about $430{\mu}m{\times}350{\mu}m$. According to measurement results, we can verify that the proposed method is reasonable with regard to the enhancement of dynamic range and the better linear-in-dB characteristics.

• Journal of the Korea Society of Computer and Information
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• v.10 no.5 s.37
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• pp.123-132
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• 2005

In this Paper, we present an improvement of switch node for wavelength multiplex optical network. Currently because of quick increase of internet traffic a big network capacity is demanded. Wavelength multiplex optical network Provides the data transfer of high speed and the transparent characteristic of the data. Therefore optic network configuration is the most powerful technology in the future. It will be able to control the massive traffic from the optical network in order to transmit the multimedia information of very many quantify. Consequently the node where the traffic control is Possible, is demanded. The optical switch node which manages efficiently the multiple wavelength was Proposed. This switch is composed of a optical switch module for switching and a wavelength converter module for wavelength conversion. It will be able to compose the switch fabric without optical/electro or electro/optical conversion using optical MEMS(Micro Electro Mechanical Switches) module. Finally, we present the good test result regarding the operational qualify of the switch fabric and the performance of optical signal from the switch node. The proposed switch node of the optic network will be able to control the massive traffic with all optical.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.914-923
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• 2009

Helix antennas have been widely applied to satellite TT&C, data communication and GPS receiver systems onboard military, remote sensing and communication purpose satellites. The helix antennas are known to be convenient to control impedance and radiation coverage characteristics with a maximum directivity in satellite z-axis. Waveguide horn is commonly used for radar system that needs ultra-wideband pulse for exploration ground radar and electromagnetic disability measurement etc. It has high efficiency and low reflection characteristics provided by the low-profile shape and suppressed radiation distortion. In this paper, a waveguide horn structure incorporated with helix antenna design is proposed for satellite applications that require ultra-wideband pulse radar and high rate RF data communication link to ground station over wide coverage area. The main design concern is to synthesize variable beam forming pattern based on modified horn-helix combination helicone structure such that multi-mission antenna is implemented applicable for TT&C, earth observation, high data rate transmission. Waveguide horn helps to reduce the overall antenna structure size by introduction fold type reflector connected to the tapered helix antenna. The next generation KOMPSAT satellite currently under development requires high-performance precision attitude control system. We present an initial design of a hybrid hern-helix antenna structure suitable for efficient RF communication module design of multi-purpose satellite systems.

• Journal of the Korea Computer Graphics Society
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• v.23 no.3
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• pp.1-8
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• 2017

In this paper, we introduce a technique to retarget human motion data to the humanoid body in a constrained environment. We assume that the given motion data includes detailed interactions such as holding the object by hand or avoiding obstacles. In addition, we assume that the humanoid joint structure is different from the human joint structure, and the shape of the surrounding environment is different from that at the time of the original motion. Under such a condition, it is also difficult to preserve the context of the interaction shown in the original motion data, if the retargeting technique that considers only the change of the body shape. Our approach is to separate the problem into two smaller problems and solve them independently. One is to retarget motion data to a new skeleton, and the other is to preserve the context of interactions. We first retarget the given human motion data to the target humanoid body ignoring the interaction with the environment. Then, we precisely deform the shape of the environmental model to match with the humanoid motion so that the original interaction is reproduced. Finally, we set spatial constraints between the humanoid body and the environmental model, and restore the environmental model to the original shape. To demonstrate the usefulness of our method, we conducted an experiment by using the Boston Dynamic's Atlas robot. We expected that out method can help the humanoid motion tracking problem in the future.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.12B
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• pp.779-789
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• 2007

This paper presents an architecture of UPnP Bridge for interconnecting Non-lP devices with heterogeneous network interfaces to UPnP devices on UPnP networks. The proposed UPnP Bridge provides a Virtual UPnP device that performs generic UPnP Device's functionalities on behalf of Non-lP device. This paper defines 3 types of descriptions, Device Description, Message Field Description, and Extended UPnP Service Description in order to reduce the amount of effort required to connect a non-lP device with a new interface or message format to UPnP network. By these three types of descriptions and Message conversion module, developers for Non-lP devices can easily connect the devices to UPnP network without additional programming. So UPnP control point controls Non-lP devices as generic UPnP device. Some experiments validate the proposed architecture, which are performed on a test bed consisting of UPnP network the proposed bridge, and non-lP devices with CAN and RS232 interfaces.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.206-206
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• 2008

압전소자를 이용한 초음파 모터는 전자기적 원리로 동작하는 기존의 모터에 비해 구조가 간단하고 소형, 경량화가 가능하며 저속에서 큰 토크가 가능하고 ${\mu}m$단위 까지 정밀제어가 가능하다는 장점 등으로 인해 그 응용분야가 점차 확대되고 있다. 초음파 모터의 원리는 수평과 수직방향에서 변위가 타원형 운동을 형성하는 것이다. 따라서 선택한 타원운동의 방식에 의해서 모터의 형상이 달라진다. 초음파 모터는 액츄에이터를 사용하여 만들기 때문에 액츄에이터의 특성은 모터의 타원변위나 토크에 영향을 미친다. 단판형 액츄에이터에 비하여 적층 액츄에이터는 입력 임피던스를 낮추어 낮은 구동전압에서 구동이 가능하며 큰 변위와 토크를 발생하기 때문에 진동자의 수명 향상과 구동전압을 낮추기에 적합하다. 적층 액츄에이터는 변위량이나 응력 등을 개선하기 위해서 전기기계 결합계수(kp) 및 압전 d상수가 큰 재료가 요구되며, 고전압에서 장시간 구동 시 마찰에 의한 열손실을 감소시키기 위해 높은 기계적 품질계수(Qm)를 가져야한다. 적층 시 내부전극으로 사용하는 Pd, Pt가 함유된 전극은 가격이 비싸 제조비용을 상승시킨다. 상대적으로 값싼 Ag전극을 사용하면 비용절감을 할 수 있지만 융점이 낮아서 저온소결이 불가피하다. 따라서, 특성이 우수한 적층 액츄에이터를 제조하기 위해서 저손실, 저온소결 할 수 있는 액츄에이터 재료가 필요한 실정이다. L1-B4 혈 선혈 초음파 모터는 L1모드와 B4모드의 공진 주파수가 일치하여야 큰 변위를 얻을 수 있는데 이전의 논문에서 Atila를 이용한 시뮬레이션 결과를 분석한 봐 있다. 적층 액츄에이터의 층수를 5,7,9,11,13,15층으로 하여 L1-B4모드에서의 공진주파수를 비교한 결과 13 층일 때 두 모드가 비슷한 공진주파수를 보였고, 티원변위궤적도 다른 층수에 비해 크게 나타났다. 본 연구에서는 시뮬레이션 결과 가장 좋은 특성을 보인 13층 액츄에이터로 선형 초음파 모터를 제작하였다. 또한, 액츄에이터는 압전 및 유전특성이 우수한 저온소결 PZW-PMN-PZT세라믹을 이용하여 제작하였고, 내부전극으로 Ag전극을 사용하였다. 제작된 13 층 선형초음파모터를 가지고 프리로드 및 전압에 따른 속도를 조사하였고, 시뮬레이션 결과와 비교해 보았다.