• Current Photovoltaic Research
• /
• v.10 no.1
• /
• pp.1-5
• /
• 2022

Bifacial photovoltaic (PV) technology has received considerable attention in recent years due to the potential to achieve a higher annual energy yield compared to its monofacial PV systems. In this study, we fabricated the bifacial c-Si PV module with a shingled design using the conventional patterned bifacial solar cells. The shingled design PV module has recently attracted attention as a high-power module. Compared to the conventional module, it can have a much more active area due to the busbar-free structure. We employed the transparent backsheet for a light reception at the rear side of the PV module. Finally, we achieved a conversion power of 453.9 W for a 1300 mm × 2000 mm area. Moreover, we perform reliability tests to verify the durability of our Shingled Design Bifacial c-Si Photovoltaic module.

• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.39 no.1
• /
• pp.31-36
• /
• 2002

Low energy boron ions were implanted into the preamorphized and crystalline silicon substrates to form 0.2${\mu}m$ $p^+-n$ junctions. The rapid thermal annealing(RTA) was used to annihilate the crystal defects due to implantation and to activate the implanted boron ions, and the furnace annealing was employed to reflow the BPSG(bolo-phosphosilicate glass). The implantation conditions for Gepreamorphization were the energy of 45keV and the dose of 3$\times$1014cm-2. BF2 ions employed as a p-type dopant were implanted with the energy of 20keV and the dose of 2$\times$1015cm-2. The thermal conditions of RTA and furnace annealing were $1000^{\circ}C$/10sec and $850^{\circ}C$/40min, respectively. The junction depths were measured by SIMS and ASR techniques, and the 4-point probe was used to measure the sheet resistances. The electrical characteristics were analyzed via the leakage currents of the fabricated diodes. The single thermal processing with RTA produced shallow junctions of good qualities, and the thermal treatment sequence of furnace anneal and RTA yielded better junction characteristics than that of RTA and furnace anneal.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.5
• /
• pp.16-22
• /
• 2002

This paper suggests the optimum processing conditions for obtaining good quality $P^{+}$-n shallow junctions formed by pre-amorphization and furnace annealing(FA) to reflow BPSG(bore phosphosilicate glass). $BF_2$ions, the p-type dopant, were implanted with the energy of 20keV and the dose of 2$\times$10$^{15}$ cm$^{-2}$ into the substrates pre-amorphized by As or Ge ions with 45keV, 3$\times$$10^{14}$ $cm^{-2}$. High temperature annealings were performed with a furnace and a rapid thermal annealer. The temperature range of RTA was 950~$1050^{\circ}C$, and the furnace annealing was employed for BPSG reflow with the temperature of $850^{\circ}C$ for 40 minutes. To characterize the formed junctions, junction depth, sheet resistance and diode leakage current were measured. Considering the preamorphization species, Ge ion exhibited better results than As ion. Samples preamorphized with Ge ion and annealed with $1000^{\circ}C$ RTA showed the most excellent characteristics. When FA was included, Ge preamorphization with $1050^{\circ}C$ RTA plus FA showed the lowest product of sheet resistance and junction depth and exhibited the lowest leakage currents.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.4
• /
• pp.7-12
• /
• 2008

This paper presents a lateral resistive contact RF MEMS switch using comb drive. Our goal was to fabricate the RF MEMS switch with high reliability and good RF characteristics for front end module in wireless transceiver system. Therefore, comb drive is used for large contact force in order to achieve low insertion loss and small off-state capacitance in order to achieve high isolation. The single crystalline silicon is used for mechanical reliability. As a result, the developed switch showed insertion loss less than 0.44 dB at 2 GHz, isolation greater than 60 dB, and low actuation voltage at 26 V.

• Journal of the Korea Computer Industry Society
• /
• v.6 no.5
• /
• pp.757-766
• /
• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.25 no.11
• /
• pp.1358-1366
• /
• 1988

The dual dielectric films have been grown on single-crystalline silicon substrates with the thickness ranging from 125A to 180A at various gas and temperature conditions by using rapid thermal process that included independent nitridation step. The film characteristics and their dependence on the contents of the hydrochloric gas and the processing time have been studied. By the addition of the hydrochloric gas, the initial oxide thickness was significantly changed, but after sequential nitridation processes the thickness of the films was nevertheless a little bit varied within 10A. All the samples of the dual dielectric films show the increased breakdown voltages in proportion to the additive contents of the hydrochloric gas and also show the higher breakdown strengths than the thermal oxide and nitrided oxide films grown by the conventional furnance process or the rapid thermal nitridation process that was composed of the dependent nitridation cycles.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.25 no.11
• /
• pp.1350-1357
• /
• 1988

The dual dielectric films have been grown on single-crystalline silicon substrates with the thickness ranging from 125A to 180A at various gas and temperature conditions by using rapid thermal process that included independent nitridation step. The film characteristics and their dependence on the contents of the hydrochloric gas and the processing time have been studied. By the addition of the hydrochloric gas, the initial oxide thickness was significantly changed, but after sequential nitridation processes the thickness of the films was nevertheless a little bit varied within 10A. All the samples of the dual dielectric films show the increased breakdown voltages in proportion to the additive contents of the hydrochloric gas and also show the higher breakdown strengths than the thermal oxide and nitrided oxide films grown by the conventional furnance process or the rapid thermal nitridation process that was composed of the dependent nitridation cycles.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.17 no.9
• /
• pp.916-923
• /
• 2004

In this paper, the strained Si$_{0.9}$Ge$_{0.1}$ epitaxial layers grown by a reduced pressure chemical vapor deposition (RPCVD) on Si (100) were characterized by Rutherford backscattering spectrometery (RBS) for the fabrication of an SiGe heterojunction bipolar transistor(HBT). RBS spectra of the ${Si}_0.9{Ge}_0.1$epitaxial layers grown on the Si substrates which were implanted with the phosphorus (P) ion and annealed at a temperature between $850^{\circ}C$ - $1000^{\circ}C$ for 30min were analyzed to investigate the post thermal annealing effect on the grown${Si}_0.9{Ge}_0.1$epitaxial layer quality. Although a damage of the substrates by P ion-implantation might be cause of the increase of RBS yield ratios, but any defects such as dislocation or stacking fault in the grown ${Si}_0.9{Ge}_0.1$ epitaxial layer were not found in transmission electron microscope (TEM) photographs. The post high temperature rapid thermal annealing (RTA) effects on the crystalline quality of the ${Si}_0.9{Ge}_0.1$ epitaxial layers were also analyzed by RBS. The changes in the RBS yield ratios were negligible for RTA a temperature between $900^{\circ}C$ - $1000^{\circ}C$for 20 sec, or $950^{\circ}C$for 20 sec - 60 sec. A SiGe HBT array shows a good Gummel characteristics with post RTA at $950^{\circ}C$ for 20 sec.sec.sec.

• Journal of the Korean Solar Energy Society
• /
• v.31 no.1
• /
• pp.37-43
• /
• 2011

In this paper, the optimized doping condition of crystalline silicon solar cells with $156{\times}156\;mm^2$ area was studied. To optimize the drive-in temperature in the doping process, the other conditions except variable drive-in temperature were fixed. These conditions were obtained in previous studies. After etching$7\;{\mu}m$ of the surface to form the pyramidal structure, the silicon nitride deposited by the PECVD had 75~80nm thickness and 2 to 2.1 for a refractive index. The silver and aluminium electrodes for front and back sheet, respectively, were formed by screen-printing method, followed by firing in 400-425-450-550-$850^{\circ}C$ five-zone temperature conditions to make the ohmic contact. Drive-in temperature was changed in range of $830^{\circ}C$ to $890^{\circ}C$to obtain the sheet resistance $30{\sim}70\;{\Omega}/{\box}$ with $10\;\Omega}/{\box}$ intervals. Solar cell made in $890^{\circ}C$ as the drive-in temperature revealed 17.1% conversion efficiency which is best in this study. This solar cells showed $34.4\;mA/cm^2$ of the current density, 627 mV of the open circuit voltage and 79.3% of the fill factor.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.294-294
• /
• 2013

소수성을 띄는 표면은 자연으로부터 시작된 연구이다. 연잎, 소금쟁이 다리, 매미 날개 등 많은 자연의 표면은 150o보다 높은 접촉각을 지니기 때문에 물에 대한 반발이 심해져 약간의 기울임에도 쉽게 물방울이 굴러 떨어지고 이때 먼지를 제거할 수 있다. 자연현상을 이용해 물질 표면의 소수성 제어에 대한 다양한 연구가 진행 중이다. 친수성과 소수성은 일반적으로 표면에서 물방울의 contact angle 측정으로 확인 할 수 있다. Contact angle이 $90^{\circ}$ 작을 경우 친수성, $90^{\circ}$보다 클 경우 소수성이라고 한다. 이러한 기술을 이용해서 solar cell, 자동차 유리, 건물외벽, 등 다양한 분야에서 사용하고 있으며, 소수성 구조를 만드는 방법으로는 laser ablation, wet etching, 리소그라피 공정이 있는데, laser ablation의 경우 가격이 비싸다는 단점을 가지고 있으며, 반면 가격이 저렴한 wet etching의 경우 제어가 힘들다는 단점을 지니고 있다. 리소그라피 공정은 비싼 비용과 시간을 소비해야 하는 단점을 지니고 있다. 본 연구에서는 이러한 단점들을 개선하기 위해 공정 시간의 감소와, 저 비용으로 제작이 가능한 RIE (Recative Ion Etching)로 피라미드 구조를 만들었다. 형성된 구조물에 투명하고 균일하며, 낮은 계면에너지를 갖고 있는 PDMS (polydimethelsiloxine)로 mold을 수행하였다. RIE를 이용한 표면 구조는 Gas, Flow rate, Pressure, Power, Time 등을 조절하여 단결정 실리콘 기판 위에 피라미드의 크기를 조절하였다. 피라미드의 크기가 커짐에 따라 물과 PDMS가 닿는 면적이 줄어들면서 높은 소수성을 가지게 되는데, 높은 소수성 구조를 가지는 피라미드 형상을 찾기 위한 실험을 진행하였다. RIE 조건은 Flow rate: 30 sccm, Temperature: $10^{\circ}C$ Pressure: 100 mTorr, Power: 200 W, Process Time: 5~50 min으로 조절하며 공정을 수행하였고 RIE공정 후 SAMs (Self-Assembly Monolayers)을 진행하였으며, 마지막으로 PDMS를 이용하여 mold공정을 진행하였다. 그리고 SEM (Scanning Electron Microscope)장비를 이용하여 Etching된 단면을 관찰하였으며, 접촉각을 측정하였다. Process Time을 50 min로 공정하였을 때, 측정된 접촉각은 $134^{\circ}$였다.