• The Transactions of the Korea Information Processing Society
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• v.5 no.8
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• pp.2164-2178
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• 1998

본 논문에서는 한 사이클에 여러 개의 명령들이 다중 이슈되어 명령어 수준에서 병렬처리되는 ILP 프로세서의 성능을 측정하고 평가하는 시스템을 개발한다. 개발되는 시스템은 C 컴파일러와 시뮬레이터로 구성된다. C 컴파일러는 C 소스 프로그램을 입력으로 받아 3-주소 코드형태의 중간언어를 생성한다. 생성된 중간언어는 ILP 프로세서의 환경 파라미터와 함께 시뮬레이터에 입력되어 시뮬레이션된 후 메모리 내용, 수행된 클럭 수 및 명령 트레이스, 수행된 명령들의 동적 빈도수, 분기명령의 예측률, profiling 정보 등을 생성한다. 개발된 성능측정 시스템의 동작 검증을 위하여 순차이슈 되어 정적으로 스케쥴링 되는 조건실행 방식의 성능과 분기처리 방식의 성능을 측정하여 분석한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.880-883
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• 2002

In this paper, we propose the synchronization recovery algorithm which is suitable to wireless multimedia of wireless channel situation which is being used OFDM signaling method. The basic of the suggested clock synchronization. restoration Algorithm is to getting the shock response of channel or getting the multipath strength profile through IFFT after the getting the frequency, response of deducted channel from channel deductor of receiver and to trace the location in the channel energy concentrated area of timing area. And it also analysis the start point of 64-QAM and 16-QAM if the sampling clock offset has the sample of $\pm$1-3, and we identified the occurance of performance deterioration when occures more than 2 samples of offset to compare with star point and BER performance in optimum sampling point result of BER performance checking, and we know that the recovery algorithm proposed algorithm also provide excellent synchronization characteries under frequency, selecting fading channel as result of simulation.

• Journal of IKEEE
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• v.26 no.4
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• pp.714-721
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• 2022

A phase-locked loop (PLL)-based frequency synthesizer is proposed for a system on a chip (SoC) using multi-frequency clock signals. The proposed PLL-based frequency synthesizer consists of a charge pump PLL which is implemented by a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage controlled oscillator (VCO), and a frequency divider, and an edge combiner. The PLL outputs a 12-phase clock by a VCO using six differential delay cells. The edge combiner synthesizes the frequency of the output clock through edge combining and frequency division of the 12-phase output clock of the PLL. The proposed PLL-based frequency synthesizer is designed using a 55-nm CMOS process with a 1.2-V supply voltage. It outputs three clocks with frequencies of 166 MHz, 83 MHz and 124.5MHz for a reference clock with a frequency of 20.75 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.71-81
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• 2008

In this paper, we propose a novel Globally Asynchronous, Locally Dynamic System(GALDS) bus and demonstrate its performance. The proposed GALDS bus is the bidirectional multitasking bus with the segmented bus architecture supporting the concurrent operation of multi-masters and multi-slaves. By analyzing system tasks, the bus architecture chooses the optimal frequency for each If among multiples of bus frequency and thus we can reduce the overall power consumption. For efficient data communications between IPs operating in different frequencies, we designed an asynchronous and bidirectional FIFO based on an asynchronous wrapper with hand-shaking interface. In addition, since systems can be easily expandable by inserting bus segments, the proposed architecture has advantages in IP reusability and structural flexibility As a test example, a four-segment bus haying four masters and four slaves were designed by using Verilog HDL. We demonstrate multitasking operations with read/write data transfers by simulation when the ratios of operation frequency are 1:1, 1:2, 1:4 and 1:8. The data transfer mode is a 16 burst increment mode compatible with Advanced Microcontroller Bus Architecture(AMBA). The maximum operation latency of the proposed GALDS bus is 22 clock cycles for the bus write operation, and 44 clock cycles for read.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.1-7
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• 2002

This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. An advanced multi-structured PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, in which it shows an excellent functionalities in terms of the jitter noises by designing its circuit with the exact dead zone and duty cycle. Our new designed adaptive charge pump in the loop filter of a PLL can improve an acquisition characteristic by adaptively increasing of current. The Hspice simulation is done to evaluate the performance of the proposed circuit. Simulation result shows that our PLL has under 0.01ns in the dead zone, no influence from the duty cycle of input signals and under 50ns in the acquisition time. This circuit will be able to be used in develops of high-performance microprocessors and digital systems.  

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.1
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• pp.18-25
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• 2018

In this paper, we present a low-power implementation of the multi-channel hearing aid system using a general-purpose DSP chip. The system includes an acoustic amplification algorithm based on Wide Dynamic Range Compression (WDRC), an adaptive howling canceller, and a single-channel noise reduction algorithm. To achieve a low-power implementation, each algorithm is re-constructed in forms of integer program, and the integer program is converted to the assembly program using BelaSigna(R) 250 instructions. Through experiments using the implementation system, the performance of each processing algorithm was confirmed in real-time. Also, the clock of the implementation system was measured, and it was confirmed that the entire signal processing blocks can be performed in real time at about 7.02MHz system clock.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.629-638
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• 2005

In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.3
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• pp.14-21
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• 1989

In the digital transmission equipment, the input jitter tolerance is a function of input timing recovery circuit characteristics. Especially, in the asynchronous multiplexers, it is also a function of the frame format, the buffer sizes in the synchronizer and desynchronizer, the PLL transfer function, and operating range of VCO in PLL In this paper, a new algorithm for calculating the jitter tolerance of the saynchronous digital transmission equipment is presented. With the new algorithm, we analyzed how the above factors limit the jitter tolerance in the equipment. We also measured the input jitter tolerance for a 45M-140M multiplexing equipment, whose results show the same trend with calculated tolerance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.11
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• pp.1462-1467
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• 2018

A number of algorithms for improving the image quality of low light images have been studied using a single image or multiple exposure images. The low light image is low in contrast and has a large amount of noise, which limits the identification of information of the subject. This paper proposes the hardware design of algorithms that improve the quality of low light image using 2 multiple exposure images taken with a dual camera. The proposed hardware structure is designed in real time processing in a way that does not use frame memory and line memory using transfer function. The proposed hardware design has been designed using Verilog and validated in Modelsim. Finally, when the proposed algorithm is implemented on FPGA using xc7z045-2ffg900 as the target board, the maximum operating frequency is 167.617MHz. When the image size is 1920x1080, the total clock cycle time is 2,076,601 and can be processed in real time at 80.7fps.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.05a
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• pp.102-105
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• 2013

최근 멀티코어 시스템은 컴퓨터의 성능을 향상시키기 위해 더 많은 수의 코어를 연결시키는 다중코어 시스템으로 발전하고 있다. 그러나 멀티코어 시스템은 사용하는 코어의 아키텍처 구조와 개수에 따라 성능 차이가 발생한다. 이에, 본 논문에서는 코어의 아키텍처 구조와 코어의 개수가 성능에 미치는 영향을 분석하기 위해 Tilera의 다중코어 시스템인 Tile-Gx36, TilePro64와 Intel의 x86-64 멀티코어 시스템인 Core i5의 성능을 비교하였다. 코어의 사용률이 늘어남에 따른 성능차이를 알아보기 위해 벤치마크 프로그램인 SPEC CPU 2006을 이용하여 각 시스템 내 단일코어의 성능을 측정하고, OpenMP 벤치마크 프로그램을 이용하여 시스템의 모든 코어를 사용했을 때의 입력 데이터 크기에 따른 성능을 측정하였다. 실험 결과, 단일코어에서의 성능은 정수형 데이터를 사용하여 측정하였을 경우 Core i5가 Tile-Gx36보다 약 87%, 실수형 데이터를 사용하여 측정하였을 경우 약 94% 더 빠른 것으로 나타났다. 그러나 코어 전체를 이용한 성능 결과에서는 정수형 배열 크기가 이상일 경우 Tile-Gx36 시스템의 처리 속도가 Core i5 시스템 보다 평균적으로 약 7.6배 향상됨을 확인할 수 있었다. 따라서 Tilera의 다중코어 시스템은 클럭 속도와 아키텍처 구조의 영향으로 단일코어의 성능은 떨어지나, 병렬 처리를 이용한 고속연산에서는 성능이 향상된다고 할 수 있다.